Transistor Gate Dishing Prevention via Sacrificial CMP Stop Layer
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Solution Overview
Problem
The 'Fang Issue' in semiconductor manufacturing, where dishing occurs around transistors due to the softness of the first silicon oxide layer formed by the HARP process, leading to particle agglomeration and subsequent manufacturing process disruptions.
Innovation Solution
A method involving the formation of a sacrificial layer with a selectivity ratio close to the stressed layer, used to prevent slurry particle agglomeration around gates, including silicon nitride, and a CMP process that uses the sacrificial layer and stressed layer as stop layers to avoid dishing, enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first silicon oxide layer is formed by HARP process without annealing, then the filling properties are excellent, but the layer becomes very soft and causes dishing during CMP process
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the soft first silicon oxide layer and the CMP slurry. This sacrificial layer has properties similar to the stressed layer and serves as a protective mediator during CMP, preventing the slurry from directly contacting and softening the first oxide layer, thereby eliminating dishing while preserving the excellent filling properties achieved by the HARP process
Solution Approach 2:
The sacrificial layer is formed in advance before the CMP process, covering the first silicon oxide layer that would otherwise be damaged. This preliminary protective action ensures that when CMP is performed later, the soft first oxide layer is already protected, preventing dishing from occurring during the planarization process
2Manufacturing precision
If CMP process is performed on the soft first silicon oxide layer, then planarization is achieved, but slurry particles agglomerate and cause dishing around the gate
Solution Approach 1:
The sacrificial layer acts as a mediator between the CMP slurry and the first silicon oxide layer. By having similar properties to the stressed layer, it provides a suitable surface for CMP that prevents slurry particle agglomeration, thereby eliminating dishing while still achieving the required planarization
3Manufacturing precision
If the sacrificial layer has the same material as the stressed layer, then dishing is avoided during CMP, but the manufacturing process becomes more complex
Solution Approach 1:
Instead of changing the material composition significantly, the solution adjusts the thickness parameter of the sacrificial layer to be between 50-200 nm. This parameter optimization allows the sacrificial layer to provide adequate protection against dishing during CMP while minimizing the additional process complexity, as the layer can be formed using standard deposition techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces dishing around transistors, preventing slurry particle agglomeration and improving transistor performance by using a sacrificial layer with a specific thickness and material similarity to the stressed layer, thereby addressing the 'Fang Issue' and enhancing manufacturing outcomes.
Implementation Method 1
performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer located on the gates of the transistors; and performing a third planarization process to remove the stressed layer located on the gates of the transistors
Data Source
AI summary
The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.