Paralleled Transistor Gate Driver Compensation for Parasitic Inductance
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Solution Overview
Problem
In power electronic modules with paralleled devices, inductive voltage drops occur due to stray or parasitic inductance, leading to deterioration of the gate drive voltage and unbalanced current sharing among transistors, which affects the performance of inverters and rectifiers.
Innovation Solution
The semiconductor device includes a first transistor and a second transistor coupled in parallel, with a first circuit providing a gate driver signal to the first transistor and a second circuit providing a gate driver signal to the second transistor, both configured to compensate for the voltage drop across parasitic inductance, ensuring the signals are in phase and at the same magnitude as a common driver signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If paralleled devices are used to increase current capacity, then the current handling capability is improved, but inductive voltage drops occur due to parasitic inductance causing deterioration of gate drive voltage
Solution Approach 1:
The patent applies local quality by providing individual gate driver circuits for each transistor in the paralleled configuration, rather than using a single common gate driver. Each gate driver circuit is locally positioned near its corresponding transistor and includes compensation components (inductors and resistors) specifically tailored to compensate for the parasitic inductance in that particular transistor's path. This localized approach ensures that each transistor receives a properly compensated gate drive signal, maintaining reliable operation while utilizing the high current capacity of the paralleled devices.
2Device complexity
If common gate driver signal is used for all paralleled devices, then the circuit complexity is reduced, but unbalanced current sharing occurs among transistors
Solution Approach 1:
The patent segments the gate driver function by providing separate gate driver circuits for each transistor in the paralleled configuration. Instead of using a single common gate driver, the system divides the gate driving function into multiple independent segments, each with its own compensation network. This segmentation allows each transistor to be driven independently with customized compensation, ensuring balanced current sharing while maintaining manageable circuit complexity through modular design.
3Reliability
If parasitic inductance compensation is implemented, then the gate drive voltage stability is improved, but the device complexity increases
Solution Approach 1:
The patent introduces intermediary compensation components (inductors and resistors) between the gate driver circuit and each transistor. These intermediary elements act as mediators that cancel out the adverse effects of parasitic inductance. By inserting these compensation components in series with the gate drive path, the system achieves stable gate drive voltage without requiring complex control algorithms or feedback mechanisms, thus improving reliability while keeping the added complexity relatively simple and straightforward.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that the gate signals applied to each transistor are in phase and at the same magnitude, compensating for inductive voltage drops and maintaining balanced current sharing, thereby improving the performance and reliability of power electronic modules.
Implementation Method 1
a first parasitic inductance between an emitter of the first transistor and an emitter of the second transistor
Data Source
AI summary
A semiconductor device includes a first transistor, a second transistor coupled in parallel with the first transistor, and a first parasitic inductance between an emitter of the first transistor and an emitter of the second transistor. The semiconductor device includes a first circuit configured to provide a first gate driver signal to the first transistor based on a common driver signal and a second circuit configured to provide a second gate driver signal to the second transistor based on the common driver signal. The first circuit and the second circuit are configured to compensate for a voltage drop across the first parasitic inductance such that the first gate driver signal and the second gate driver signal are in phase with and at the same magnitude as the common driver signal.