Transistor Gate Protection Against EPI Particles
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Solution Overview
Problem
Existing transistor fabrication methods with stress layers in the source and drain regions face issues such as morphology quality and performance stability due to the formation of EPI particles, which affect the accuracy and reliability of the lithography process and lead to leakage currents.
Innovation Solution
A method involving the formation of a protective layer on the side surfaces of the gate layer to prevent EPI particle formation, combined with the creation of sidewall spacers and stress layers in the fin regions, ensuring accurate morphology and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress layers are formed in the source and drain regions to improve carrier mobility, then transistor performance is improved, but EPI particles are formed on the gate layer vertexes causing morphology quality issues and leakage currents
Solution Approach 1:
A protective layer is introduced as an intermediary between the gate layer and the stress layer formation process. This protective layer prevents EPI particles from forming on the gate layer vertexes during stress layer deposition, while allowing the stress layer to still provide the necessary stress to the channel region for improved carrier mobility. After the stress layer is formed, the protective layer is removed, leaving the gate layer clean and free of EPI particles.
2Productivity
If the gate size is decreased to increase component density, then integration level is improved, but short channel effect increases and leakage current is generated
Solution Approach 1:
The patent changes the physical and chemical parameters of the channel region by forming stress layers with specific lattice structures (silicon germanium for PMOS, silicon carbide for NMOS) that induce mechanical stress in the channel. This stress modifies the carrier mobility parameter, allowing smaller gate sizes to maintain adequate electrical control and reduce leakage current despite the reduced gate dimensions.
3Reliability
If carrier mobility is increased to improve transistor drive current, then performance is improved, but the complexity of the fabrication process increases due to additional stress layer formation steps
Solution Approach 1:
The protective layer formation is merged with the existing fabrication process flow, utilizing standard deposition and etching techniques that are already part of the manufacturing sequence. The protective layer is formed, patterned, and removed using processes that can be integrated into the existing stress layer formation workflow, minimizing the addition of complex fabrication steps while still achieving the goal of preventing EPI particle formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the stability and reliability of transistors by preventing EPI particle formation and maintaining desired morphology, thereby improving the performance and yield of semiconductor devices.
Implementation Method 1
Silicon germanium and silicon share a same lattice structure, i.e., a 'diamond' configuration, and at room temperature, the lattice constant of silicon germanium is larger than that of silicon. Therefore, there is a crystal lattice mismatch between silicon and the embedded silicon germanium structures. Such a mismatch may provide a compressive stress to the channel region of the transistor; and thus improve the carrier mobility of the channel region.
Implementation Method 2
Increasing stress in the channel region of a transistor is a key to improve the carrier mobility. Therefore, increasing the stress in the channel region of a transistor may significantly improve the performance of the transistor.
Data Source
AI summary
A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer.