Transistor Gate Filling With Diffusion Barrier
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Solution Overview
Problem
Existing memory devices face challenges in reducing junction resistance and preventing impurity diffusion, which affects the reliability and performance of transistors, particularly in designs where a high concentration of impurities is required to decrease interfacial resistance.
Innovation Solution
The proposed solution involves a transistor structure with a gate filled in a semiconductor substrate, including a junction with a metal-containing layer and a first semiconductor layer doped with a high impurity concentration, and a material layer that acts as a diffusion barrier and stress applicator, positioned between the active region and the junction to prevent impurity diffusion and increase carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high concentration of impurities is introduced into the first semiconductor layer to decrease interfacial resistance, then junction resistance is reduced, but impurity diffusion into the active region occurs which degrades transistor performance
Solution Approach 1:
A material layer is introduced as an intermediary between the first semiconductor layer (doped with high concentration impurities) and the active region. This material layer acts as a diffusion barrier that prevents impurity diffusion into the active region while allowing the first semiconductor layer to maintain high impurity concentration for low junction resistance. The material layer thus mediates between the conflicting requirements of low junction resistance and prevention of impurity diffusion.
Solution Approach 2:
The junction structure is segmented into multiple layers: the active region, the material layer (diffusion barrier), and the first semiconductor layer (doped region). This segmentation allows each layer to perform its specific function independently - the material layer prevents diffusion while the doped semiconductor layer provides low resistance contact, resolving the contradiction between these two requirements.
2Reliability
If the gate is filled in the semiconductor substrate to improve transistor characteristics, then carrier mobility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The material layer is formed in advance before the gate filling process. This preliminary action prepares the diffusion barrier structure beforehand, so that when the gate is subsequently filled in the semiconductor substrate, the impurity diffusion is already prevented. This sequencing of operations simplifies the overall manufacturing process by avoiding the need for complex in-situ barrier formation during gate filling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces junction resistance, increases operating current, and enhances the reliability and performance of transistors by preventing impurity diffusion and applying stress to the channel, thereby improving the operating characteristics of memory devices.
Implementation Method 1
a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer
Implementation Method 2
the material layer includes a material which applies a stress to a channel of the transistor
Data Source
AI summary
This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region.