Transistor Gate Insulation for High Breakdown Voltage
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Solution Overview
Problem
High voltage MOS transistors, such as LDMOSFETs, face challenges in achieving high breakdown voltage while maintaining low turn-on voltage, which is crucial for efficient high voltage operation in power applications.
Innovation Solution
The transistor structure incorporates a substrate with a gate region and trenches, featuring a thicker second gate insulating layer and a gate layer with a downward protruding portion, along with doped regions and spacers, to enhance breakdown voltage and reduce turn-on voltage. This design includes a first trench for the drain region and a second trench for the source region, with specific radii and depths optimized for electric field management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate insulating layer is used to achieve high breakdown voltage, then breakdown voltage is improved, but turn-on voltage increases
Solution Approach 1:
The patent applies different thicknesses of gate insulating layers at different locations: a first gate insulating layer with first thickness and a second gate insulating layer with second thickness (greater than first thickness). This local differentiation allows the thicker layer to provide high breakdown voltage where needed while the thinner layer maintains low turn-on voltage characteristics.
Solution Approach 2:
The gate insulating layer is segmented into multiple distinct layers (first gate insulating layer and second gate insulating layer) with different thicknesses. This segmentation enables each layer to perform its specific function optimally - one layer for breakdown voltage protection and another for turn-on voltage control.
2Reliability
If the gate structure is designed for high breakdown voltage operation, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The gate structure implements local quality by positioning a thicker gate insulating layer specifically at the drain side (second gate insulating layer) while maintaining a thinner layer at the source side (first gate insulating layer). This targeted approach achieves high breakdown voltage without uniformly increasing complexity across the entire device.
Data Source
AI summary
A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.