High-Frequency Transistor Gate Layout With Lower Resistance and Capacitance
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Solution Overview
Problem
Current transistors with one-sided gate contacts exhibit high gate resistance, which limits their maximum oscillation frequency in high-frequency applications, and while double-sided gate contacts and improved BEOL metal interconnects attempt to address this, they often result in increased parasitic capacitance, making them unsuitable for high-frequency use.
Innovation Solution
A high-frequency transistor design featuring a substrate with gates and sources/drains on both sides, a unique metal layer layout with discontinuous and continuous segments, and a BEOL metal interconnect structure that reduces gate resistance and parasitic capacitance by vertically distributing the metal layers and minimizing capacitance across the active area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one-sided gate contact is used, then the device structure is simple, but the gate resistance is high
Solution Approach 1:
The gate contact structure is segmented into two separate contacts (first gate contact and second gate contact) positioned at opposite ends of the gate electrode, forming a double-sided gate contact configuration. This segmentation divides the single high-resistance contact path into two lower-resistance paths, effectively reducing the overall gate resistance while maintaining structural simplicity.
2Reliability
If double-sided gate contact is used, then the gate resistance is reduced, but the parasitic capacitance increases
Solution Approach 1:
The gate contacts are positioned in the first horizontal plane at opposite ends of the gate electrode, while the source/drain contacts are positioned in a second horizontal plane below the first plane. This vertical separation into different planes reduces the overlap area between gate and source/drain contacts, thereby minimizing parasitic capacitance while maintaining the low gate resistance benefit of double-sided contact.
3Reliability
If BEOL metal interconnect is used to directly connect gate in active area, then the gate resistance is reduced, but the parasitic capacitance from gate to source/drain increases
Solution Approach 1:
The gate contacts and source/drain contacts are separated into different vertical planes, with gate contacts in the upper plane and source/drain contacts in the lower plane. This three-dimensional arrangement reduces the capacitive coupling between gate and source/drain regions while allowing direct connection to the gate electrode, achieving low gate resistance without excessive parasitic capacitance.
Data Source
AI summary
A high frequency transistor includes a substrate, a plurality of gates, a plurality of sources/drains, a first metal layer, a plurality of source/drain contacts, and a plurality of first gate contacts. The gates extend along a first direction on a surface of the substrate, and the sources/drains are disposed in the substrate on both sides of each of the gates. The first metal layer has a first portion extending along the first direction and a second portion extending along a second direction, and the first direction is perpendicular to the second direction. The first portion is a discontinuous line segment having a discontinuous region in the second direction, and the second portion is a continuous line segment passing through the discontinuous region. The source/drain contacts are respectively connected to the first portion and the sources/drains. The first gate contacts are respectively connected to the second portion and the gates.