Hetero Junction Transistor Gate Leakage Control
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Solution Overview
Problem
In semiconductor devices with a low-resistance region in the barrier layer between the gate electrode and the channel layer, gate leakage current is a significant issue that reduces the maximum drain current and increases on-resistance, hindering the miniaturization and power efficiency of portable communication terminals.
Innovation Solution
A semiconductor device structure featuring a channel layer made of a compound semiconductor with a barrier layer having an energy band farther from the intrinsic Fermi level, a low-resistance region with impurity in the barrier layer's surface, and a gate electrode positioned above the low-resistance region through a gate insulating layer, which prevents gate leakage current by expanding or contracting the carrier depletion region in response to gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low-resistance region is provided in the barrier layer to reduce gate resistance, then gate control capability is improved, but gate leakage current increases
Solution Approach 1:
The patent applies local quality by creating a low-resistance region specifically in the barrier layer at the gate contact position, while keeping the rest of the barrier layer with high resistance. This is achieved by selectively forming an impurity region in the barrier layer beneath the gate electrode, providing different resistance characteristics in different locations to simultaneously improve gate control and reduce leakage current.
Solution Approach 2:
The patent changes the resistance parameter of the barrier layer locally by introducing impurities in a controlled manner. The low-resistance region is formed by adjusting impurity concentration in the barrier layer beneath the gate electrode, while maintaining low impurity concentration in other regions. This parameter change allows the barrier layer to have both low resistance where needed and high resistance where leakage must be prevented.
2Speed
If impurity concentration is reduced in the channel layer to increase carrier mobility, then electron mobility is improved, but on-resistance increases
Solution Approach 1:
The patent segments the barrier layer into different functional regions: a low-resistance region beneath the gate electrode for good ohmic contact and current collection, and high-resistance regions in other areas to prevent leakage. This segmentation allows the channel layer to maintain low impurity concentration for high mobility while the barrier layer provides the necessary resistance characteristics for low on-resistance.
Solution Approach 2:
The barrier layer acts as an intermediary between the gate electrode and the channel layer. By controlling impurity distribution in the barrier layer, it mediates between the need for low contact resistance at the gate and the need for high resistance to prevent leakage, without requiring changes to the channel layer impurity concentration that would affect carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the maximum drain current by preventing gate leakage and reducing on-resistance, enabling the miniaturization of devices and reducing power consumption in portable communication systems.
Implementation Method 1
a gate insulating layer provided on the low-resistance region, and a gate electrode provided above the low-resistance region through the gate insulating layer
Implementation Method 2
there is a junction field-effect transistor (JPHEMT: junction pseudo-morphic high electron mobility transistor)... the hetero junction of a channel layer made of, for example, InGaAs and a barrier layer (AlGaAs) made of AlGaAs having a wider bandgap than the channel layer (InGaAs). A two-dimensional electron gas layer in which electrons to be carriers are shut with high concentration is formed in an interface on the barrier layer's side in the channel layer
Implementation Method 3
as the p-n junction is formed by providing the low-resistance region in the barrier layer, forward current flows in the p-n junction when a positive voltage exceeding a built-in voltage is applied
Data Source
AI summary
A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; a gate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.