Planar Transistor Gate Layout for Lower Leakage Current
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Solution Overview
Problem
Conventional planar channel transistors face increased power consumption due to leakage current caused by concentrated electric fields between the source/drain and carrier channel, which is exacerbated by the decreasing size and channel length of these devices.
Innovation Solution
The transistor device features a gate structure with wing portions that form obtuse angles with the body and head portions, creating rounded edges that mitigate electric field crowding, reducing leakage current and power consumption while increasing driving current through slanted sides with respect to the source/drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size and channel length of conventional planar channel transistor are reduced, then the transistor size decreases, but leakage current increases due to concentrated electric field at the boundary between isolation structure and active region
Solution Approach 1:
The gate structure employs rounded corners instead of sharp right angles at the intersections of gate portions and isolation structures. This curvature design distributes the electric field more uniformly across the interface between the active region and isolation structure, preventing field concentration that would otherwise occur at sharp corners. The rounded geometry effectively reduces leakage current while maintaining the scaled-down transistor dimensions.
2Length of moving object
If conventional planar channel transistor is used with reduced channel length, then device miniaturization is achieved, but power consumption increases due to leakage current
Solution Approach 1:
The rounded corner design of the gate structure eliminates sharp angles where electric field concentration occurs. By curving the corners at the intersection of gate portions and isolation structures, the patent distributes the electric field more evenly, reducing leakage current and thereby lowering power consumption in miniaturized transistors with reduced channel length.
3Ease of manufacture
If sharp corner design is used in gate structure, then manufacturing is simpler, but electric field concentration occurs at the boundary between isolation structure and active region
Solution Approach 1:
The patent implements rounded corners in the gate structure where gate portions intersect with isolation structures. This curvature replaces sharp angles, distributing the electric field more uniformly across the interface. While slightly more complex than sharp corner fabrication, the rounded design effectively eliminates electric field concentration and the associated leakage current problems.
Data Source
AI summary
The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.