Transistor Gate Oxide Integrity via Rear Surface Insulation
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Solution Overview
Problem
Conventional semiconductor manufacturing methods result in MOS transistors with poor gate oxide integrity and low voltage withstand capabilities due to exposure of the substrate's rear surface, leading to electrical connections and corrosion issues during high-energy plasma processes.
Innovation Solution
A method involving the formation of stressed layers on NMOS and PMOS transistors, followed by selective removal and annealing, and the deposition of a corrosion-resistant insulating structure on the substrate's rear surface to prevent corrosion and electrical connections, along with planarization processes to maintain gate oxide integrity and enhance voltage withstand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the substrate's rear surface is exposed during manufacturing, then manufacturing process access is improved, but gate oxide integrity deteriorates due to corrosion and electrical connections from plasma bombardment
Solution Approach 1:
A corrosion-resistant insulating structure is introduced as an intermediary layer on the substrate's rear surface. This mediator protects the substrate from direct exposure to corrosive chemicals and plasma bombardment during high-energy manufacturing processes, while still allowing the manufacturing processes to proceed. The insulating structure acts as a protective barrier that prevents both chemical corrosion and electrical connections, thereby maintaining gate oxide integrity without compromising manufacturing accessibility.
2Manufacturing precision
If high-energy plasma processes are applied to the substrate, then manufacturing precision is improved, but voltage withstand capability deteriorates due to electrical connections and corrosion
Solution Approach 1:
The corrosion-resistant insulating structure is formed on the substrate's rear surface before the high-energy plasma processes are applied. This preliminary protective action ensures that when plasma bombardment and other high-energy manufacturing processes occur, the substrate is already protected. The pre-formed insulating layer prevents corrosion and electrical connections that would otherwise compromise voltage withstand capability, allowing high-energy plasma processes to be used for improved manufacturing precision without sacrificing transistor reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables transistors to withstand high voltages while maintaining good gate oxide integrity by preventing corrosion and electrical connections, ensuring improved electrical performance.
Implementation Method 1
A direction of the stress is parallel to a length direction of the channel and the stress may be a tensile stress or a compressive stress. Generally, the tensile stress makes atoms arranged sparsely in the channel so that mobility of electrons is promoted.
Implementation Method 2
annealing the substrate
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a substrate having an NMOS transistor and a PMOS transistor formed thereon, forming a stressed layer that covers the transistors, and selectively removing the stressed layer on the PMOS transistor. The method further includes annealing the substrate, removing the remaining stressed layer, forming a dielectric layer structure on the transistors; and performing a first planarization process on the dielectric layer structure. The method also includes forming a corrosion-resistant insulating structure on a rear surface of the substrate, and performing a second planarization process on the dielectric layer structure. The semiconductor device thus formed can withstand high voltages while maintaining gate oxide integrity.