Power Transistor Gate Pulsing for Capacitive Load Startup

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Solution Overview

Problem

Charging high capacitive loads in electronic circuits during power-up poses challenges, as high current density can trigger protective mechanisms or thermal instability, while low current density may deteriorate power transistors.

Innovation Solution

A method involving pulsed signals with varying wait times and current thresholds is applied to the gate of a power transistor, monitoring voltage and current levels to manage capacitive load charging, preventing thermal instability and short-circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a high density of current is applied across the power transistor during supply, then the charging speed of capacitive loads is improved, but the risk of short-circuit and thermal instability increases

Engineering Contradiction:
Improvecharging speedVSAvoidshort-circuit risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies periodic pulsed signals to the power transistor gate instead of continuous current. The control circuit generates pulses with specific duty cycles and frequencies that allow the capacitive load to charge progressively while providing rest periods that prevent thermal accumulation and reduce short-circuit risk. This periodic action enables fast charging without sustained high current density.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent dynamically adjusts the pulse characteristics (amplitude, width, frequency) based on the charging state of the capacitive load. The control circuit monitors the voltage across the load and modifies the pulse parameters in real-time, increasing charging speed when voltage is low and reducing pulses when approaching the target voltage, thereby optimizing both speed and reliability throughout the charging process.

Inventive Principle:
Principle #15Dynamics

2Productivity

If a high density of current is applied across the power transistor, then the charging speed of capacitive loads is improved, but the stress on components including the power transistor increases

Engineering Contradiction:
Improvecharging speedVSAvoidcomponent stress
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

By using periodic pulses instead of continuous current, the patent reduces cumulative stress on the power transistor and other components. The pulsed nature allows thermal dissipation between pulses and reduces electromagnetic stress, enabling fast charging without proportionally increasing component stress.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies partial current density through controlled pulse width modulation. Instead of applying full continuous current that would cause excessive stress, the system applies current in controlled portions through pulses with duty cycles less than 100%, achieving sufficient charging speed while keeping component stress within safe limits.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If a too low density of current is applied, then the thermal instability risk is reduced, but the power transistor may be deteriorated

Engineering Contradiction:
Improvethermal stabilityVSAvoidpower transistor health
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The periodic pulsed signals provide optimal thermal management by allowing the power transistor to cool between pulses while still delivering sufficient total current over time. The pulse frequency and duty cycle are chosen to keep the transistor in its safe operating area, preventing both thermal instability and degradation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the current delivery parameters from continuous to pulsed, and dynamically adjusts pulse characteristics based on operating conditions. This parameter transformation enables the system to operate in the optimal region that balances thermal stability with transistor health, avoiding both excessive current and insufficient current scenarios.

Inventive Principle:
Principle #35Parameter changes

4Loss of time

If a fast charging method is used, then the functional time is reduced, but the risk of triggering protective mechanisms increases

Engineering Contradiction:
Improvefunctional timeVSAvoidprotective mechanism triggering
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The periodic pulsed charging method achieves fast charging while avoiding continuous high current that would trigger protective mechanisms. The pulses are designed with appropriate amplitude and width to charge the capacitive load quickly without exceeding the threshold that would activate short-circuit protection or other safety mechanisms.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The control circuit incorporates feedback monitoring of the voltage across the capacitive load and adjusts the pulse parameters accordingly. This feedback mechanism ensures that charging proceeds quickly while automatically preventing conditions that would trigger protective mechanisms, as the system responds in real-time to the actual charging state.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12488829B2Method and circuit for power-up of an electronic circuit
Publication Date: 2025.12.02 STMICROELECTRONICS (ROUSSET) SAS
  • US12488829B2 patent drawing
  • US12488829B2 patent drawing
  • US12488829B2 patent drawing

AI summary

The present disclosure relates to a method comprising: applying, by a control circuit, a first pulsed signal, consisting of sequential first voltage pulses, to the gate of a power transistor supplying a capacitive load of the circuit, the pulses of the first pulsed signal being separated from each other by a first wait time; further to one or more of the pulses of the first signal, making a comparison, by a comparator, of the value of the voltage across the capacitive load with a first voltage threshold value; and, if the first voltage threshold value is exceeded, applying a second pulsed signal, consisting of sequential second voltage pulses, to the gate of the power transistor, the pulses of the second pulsed signal being separated from each other by a second wait time shorter than the first wait time.