Transistor Gate Structure Recess Design for Low On-State Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOS transistors face challenges in minimizing on-state resistance (Ron) while maintaining computing power and manufacturing simplicity, often resulting in large sizes and high costs due to complex structures.
Innovation Solution
The transistor device incorporates a substrate with recesses and a gate structure that includes semiconductor and conductor members, where the gate structure is partially disposed inside recesses to maximize effective channel width, using an oxide and polysilicon member configuration, and an insulating isolation member to minimize Ron without complicating the structure or manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel width of the MOS transistor is configured substantially large to minimize Ron, then the on-state resistance is reduced, but the device size and manufacturing complexity increase
Solution Approach 1:
The gate structure is divided into two portions: a first gate structure portion positioned inside the recess and a second gate structure portion positioned outside the recess. This spatial division in the vertical dimension allows the channel width to be effectively increased without proportionally increasing the planar device footprint, thereby reducing Ron while controlling device size.
Solution Approach 2:
The first gate structure portion is nested within the recess formed in the substrate. This nesting approach allows the gate to extend into the substrate volume, effectively increasing the channel width without increasing the planar area occupied by the device, thus minimizing Ron while maintaining compact device size.
2Reliability
If alternative MOS transistor configurations are used to minimize Ron, then the on-state resistance is reduced, but the structure becomes substantially complicated and costs increase
Solution Approach 1:
The gate structure is segmented into two distinct portions: a first gate structure portion inside the recess and a second gate structure portion outside the recess. This segmentation allows each portion to be optimized independently for its specific function while maintaining overall structural simplicity and ease of manufacturing.
Solution Approach 2:
The recess is positioned specifically in the active region of the substrate where the channel is formed, allowing the gate structure to locally extend into the substrate only where needed to increase channel width. This localized modification maintains simplicity in other regions of the device structure.
Data Source
AI summary
A transistor device may include a substrate that has a recess and a substrate surface, wherein the recess is recessed with respect to the substrate surface. The transistor device may further include a source and a drain that overlap the substrate. The transistor device may further include a gate structure that has a first gate structure portion and a second gate structure portion, wherein the first gate structure portion is positioned inside the recess, and wherein the second gate structure portion is connected to the first gate structure and is positioned outside the first recess.