Transistor Gate Structure With Small Footing for Replacement Gate Processing

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Solution Overview

Problem

As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in processing operations such as the replacement gate process and epitaxial growth, necessitating improvements in the formation of transistor structures.

Innovation Solution

The formation of dummy gates with a small footing profile around semiconductor fins and nanostructures, which are subsequently removed in a replacement gate process, enhances the processing window for subsequent operations like epitaxial growth by maintaining precise control over the gate structure dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional processing challenges arise in operations such as replacement gate process and epitaxial growth

Engineering Contradiction:
Improveintegration densityVSAvoidprocessing difficulty
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The method performs preliminary actions by forming dummy gates with a small footing profile before the replacement gate process and epitaxial growth operations. This preliminary structuring creates a controlled template that guides subsequent processing steps, enabling precise formation of source/drain regions and gate structures even at reduced feature sizes, thereby resolving the processing challenges associated with higher integration density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes critical parameters by controlling the footing profile dimension of dummy gates to be smaller than conventional structures. This parameter modification (reducing footing profile while maintaining gate functionality) allows the processing window for epitaxial growth and replacement gate operations to be maintained or expanded, enabling successful manufacturing at smaller feature sizes required for increased integration density

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If dummy gates with small footing profile are formed to maintain control over gate structure dimensions, then the processing window for subsequent operations is increased, but additional processing steps are required

Engineering Contradiction:
Improvegate structure dimension controlVSAvoidprocessing steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dummy gates serve multiple functions: they act as temporary structural elements during fabrication, define the footing profile for source/drain region formation, and serve as templates for the replacement gate process. This multi-functionality consolidates several processing objectives into a single structural element, achieving precise gate dimension control without proportionally increasing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The dummy gates are designed as temporary, disposable structures that are formed precisely for their intended purpose and then removed in the replacement gate process. This approach allows use of simple, easily-formed materials and structures that sacrifice themselves to enable more complex final gate structures, achieving high manufacturing precision without permanently increasing device complexity

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20250267895A1Transistor gate structures
Publication Date: 2025.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250267895A1 patent drawing
  • US20250267895A1 patent drawing
  • US20250267895A1 patent drawing

AI summary

In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.