Transistor Gate Spacer Formation via Selective Etching
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Solution Overview
Problem
Current techniques for producing transistor gate spacers are complex and lack precise control over etching phases, leading to inconsistent shapes and potential damage to thin semiconductor layers, especially in nanoscale transistors.
Innovation Solution
A method involving successive steps of dielectric layer formation, anisotropic etching, surface layer modification, and selective etching is used to produce spacers, allowing for precise control over the shape and location of etching, thereby protecting the semiconductor layer and enabling the formation of spacers with a recessed foot without damaging the underlying material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used to form spacers, then spacer formation is achieved, but precise control over etching phases and spacer shape is lost
Solution Approach 1:
The etching process is divided into multiple sequential phases: anisotropic etching to remove dielectric material, followed by selective etching to remove surface layer material. Each phase targets specific materials with different etching rates, enabling precise control over the spacer foot shape and dimensions without requiring complex process equipment.
Solution Approach 2:
A surface layer is deposited on the dielectric layer before etching begins. This surface layer serves as a protective mask during anisotropic etching and is subsequently removed in a controlled manner to define the spacer foot geometry, enabling precise shape control before the final etching step.
2Manufacturing precision
If aggressive etching is used to remove dielectric material, then complete dielectric removal is achieved, but damage to thin semiconductor layers occurs
Solution Approach 1:
A surface layer material is introduced as an intermediary between the dielectric layer and the semiconductor layer. During anisotropic etching, this surface layer protects the underlying thin semiconductor layer from damage while allowing complete removal of the dielectric material through selective etching processes.
Solution Approach 2:
Different etching parameters are used for different materials: aggressive parameters for removing dielectric material, and controlled parameters for removing the surface layer. The etching selectivity between materials is exploited to achieve complete dielectric removal without damaging the semiconductor layer.
3Shape
If simple spacer formation is used, then process simplicity is maintained, but recessed foot shape control is not achieved
Solution Approach 1:
The surface layer is selectively removed from specific regions to create the recessed foot shape. The etching process targets only the surface layer material at the spacer foot location, leaving the main spacer body intact, thereby achieving localized shape modification with simple process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for selective etching that preserves the semiconductor layer, enabling precise control over spacer shape and reducing defects, thus improving the production of nanoscale transistors by avoiding damage to the semiconductor material and ensuring accurate epitaxial growth of source and drain zones.
Implementation Method 1
anisotropic etching of the dielectric layer configured to partially remove the dielectric layer at the level of the peripheral zone while preserving the dielectric layer at the level of the flanks
Implementation Method 2
partial etching of the surface layer configured to completely remove the surface layer at the peripheral zone while preserving a residual part of the surface layer at the sidewalls
Data Source
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AI summary
The invention relates to the production of spacers (230) at the level of the flanks (206,207) of a transistor gate (200), comprising a step of forming a dielectric layer (231) covering the gate (200) and a peripheral area (220, 221) of a layer of semiconductor material (212) surrounding the gate (200) comprising the following steps: - formation of a surface layer (232) covering the gate (200) and the peripheral area; - partial removal of the surface layer (232) configured to completely remove the surface layer (232) at the level of the peripheral area (220, 221) while preserving a residual part (234) of the surface layer (232) at the level of the flanks (206,207); - selective etching of the dielectric layer (231) with respect to the material of the residual part (234) of the surface layer (232) and with respect to the semiconductor material (212).