3D Transistor Gate Spacer Design for Memory Sensing Margin
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Solution Overview
Problem
Semiconductor memory devices face challenges in increasing data storage capacity and data sensing margin due to the limited size of information storage elements, which are difficult to enhance without compromising the bipolar operation of the semiconductor device.
Innovation Solution
The design includes a transistor with a gate pattern on a semiconductor substrate, featuring spacer patterns and semiconductor regions with varying impurity ion concentrations and conductivity types, which increase the cross-sectional area of the gate pattern and prevent data inversion between adjacent transistors, thereby enhancing data storage capacity and sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the information storage element is formed by implanting impurity ions in the semiconductor substrate under a gate pattern, then the information storage element size is reduced, but the data sensing margin cannot be increased
Solution Approach 1:
The patent extends the information storage element vertically into the substrate, creating a deep well structure that increases storage capacity without increasing lateral footprint. This dimensional transition from 2D surface storage to 3D volumetric storage resolves the contradiction between miniaturization and sensing margin.
Solution Approach 2:
The information storage element is nested within the substrate beneath the gate pattern, with source and drain regions positioned around it. This nested configuration allows the storage element to be contained within the footprint of the transistor while maintaining adequate separation for bipolar operation.
2Area of stationary object
If the information storage element is surrounded by source and drain regions that overlap with the gate pattern, then the information storage element size is limited, but this configuration is difficult to increase data sensing margin
Solution Approach 1:
The patent positions source and drain regions in different vertical planes relative to the gate pattern, with the information storage element extending deeper into the substrate. This vertical separation allows overlap in the planar view while maintaining electrical isolation and adequate sensing margins.
Solution Approach 2:
The patent creates regions of different impurity concentrations at different locations and depths within the substrate. The information storage element has high impurity concentration for charge storage, while surrounding regions have graded concentrations to facilitate carrier injection and maintain bipolar operation without requiring precise lateral alignment.
3Area of stationary object
If reduced design rules are used to increase integration density, then device size is reduced, but data inversion between adjacent transistors occurs
Solution Approach 1:
By moving the information storage function into the vertical dimension with deep substrate wells, the patent increases the spacing required between adjacent devices in the lateral plane. This vertical separation prevents cross-talk and data inversion even when lateral dimensions are reduced according to scaled design rules.
Solution Approach 2:
The patent introduces intermediate doped regions between the information storage element and adjacent transistor structures. These intermediate regions act as buffers that prevent electrical interference and data inversion between neighboring devices, enabling closer packing without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the data storage capacity and sensing margin of semiconductor memory devices while preventing data inversion between adjacent transistors, even with reduced design rules, and applies tensile stress to the semiconductor layer for improved charge mobility.
Implementation Method 1
The dielectric layer may include an insulating material having a silicon nitride to apply tensile stress to the semiconductor layer
Implementation Method 2
If the information storage element is formed by implanting impurity ions in the semiconductor substrate under a gate pattern of the transistor
Data Source
AI summary
Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.