Transistor Gate Spacer Voids for Parasitic Capacitance Reduction
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Solution Overview
Problem
As transistors are scaled to decreasing dimensions, parasitic capacitance between the gate and source/drain regions increases, reducing the overall speed of transistors and posing a challenge in achieving higher integration levels.
Innovation Solution
Incorporating voids adjacent to the sidewalls of transistor gates, which are low-dielectric-constant regions between the gates and source/drain regions, formed by removing a sacrificial material comprising silicon, boron, nitrogen, and oxygen, to alleviate parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are scaled to decreasing dimensions to achieve higher integration levels, then integration density is improved, but parasitic capacitance between gate and source/drain regions increases which reduces transistor speed
Solution Approach 1:
The patent extracts the problematic dielectric material from the region between the gate and source/drain regions by using a sacrificial material that is selectively removed. This creates a void or low-dielectric-constant region that eliminates the parasitic capacitance pathway while maintaining the physical structure needed for high integration density
Solution Approach 2:
The patent applies different dielectric properties to different regions: the void or low-k material is placed specifically in the region between gate and source/drain where parasitic capacitance is problematic, while other regions maintain their standard dielectric materials. This localized modification reduces parasitic capacitance without affecting overall device structure
2Ease of manufacture
If conventional transistor configurations are used to maintain simple manufacturing processes, then ease of manufacture is preserved, but parasitic capacitance increases which limits transistor performance
Solution Approach 1:
The sacrificial material is deposited and patterned in advance, before the gate and source/drain regions are fully formed. This preliminary structure guides subsequent processing steps and ensures the void is correctly positioned to eliminate parasitic capacitance without complicating the overall manufacturing flow
Solution Approach 2:
The sacrificial material acts as an intermediary that temporarily occupies the space where the void will eventually be. It facilitates the creation of the low-parasitic capacitance region through standard deposition and etching processes, then is removed to leave the desired structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, enhancing transistor speed and enabling higher integration levels by minimizing electrical coupling between the gate and source/drain regions.
Implementation Method 1
there may be parasitic capacitance between the gate and one or both of the source/drain regions. Such parasitic capacitance may detrimentally reduce the overall speed of the transistors
Data Source
AI summary
Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.