Transistor Gate Layout to Prevent STI-Induced Kink Effect
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Solution Overview
Problem
The formation of divots during the wet etching process in STI structures leads to sharp edges in the conductive gate material, increasing the electric field and altering the threshold voltage of transistors, known as the kink effect.
Innovation Solution
A transistor structure with a gate that does not overlap the trench isolation region, featuring a gate length shorter than the gate dielectric layer and having rounded corners, with margins of at least 30 nm from the active area edges, and a metal gate configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate is formed to overlap the trench isolation region to maximize active area utilization, then the transistor density is improved, but divots in the STI structure cause sharp edges in the conductive gate material that increase the electric field and alter the threshold voltage (kink effect)
Solution Approach 1:
The gate structure is extracted or separated from overlapping with the trench isolation region. The gate is positioned to be substantially aligned with or recessed from the active area edges, removing it from the harmful proximity to divots in the STI structure, thereby eliminating the source of the kink effect while maintaining adequate transistor density through optimized gate dimensions and spacing
Solution Approach 2:
The gate design proactively prevents the formation of sharp edges by avoiding overlap with the trench isolation region where divots form during wet etching. By positioning the gate to be aligned with or recessed from the active area edges before the wet etching process occurs, the design preemptively counteracts the potential harmful effect of divot-induced sharp edges on threshold voltage stability
2Reliability
If the gate width is reduced to avoid overlapping the trench isolation region, then the kink effect is prevented, but the effective gate control over the channel is reduced
Solution Approach 1:
The gate dimensions are optimized by adjusting the gate width to be smaller than the active area width and the gate length to be shorter than the gate dielectric layer length. These parameter changes allow the gate to avoid overlapping with the trench isolation region (preventing kink effect) while maintaining sufficient gate control through carefully selected dimensional relationships rather than simply reducing all dimensions
Data Source
AI summary
A transistor structure includes a substrate and an active area defined by a trench isolation region on the substrate. The active area includes a source region, a drain region spaced apart from the source region, and a channel region between the source region and the drain region. A gate is disposed on the channel region. The gate has a gate length that is in parallel with a source-to-drain direction and a gate width that is smaller than a width of the active area.