Transistor Gate Stack With Tungsten Liner
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Solution Overview
Problem
Transistor gates in nonvolatile memory integrated circuits face challenges with high resistance in select transistors and peripheral circuits due to the significant resistance of control lines, which affects the efficiency and performance of these circuits.
Innovation Solution
A transistor gate stack is formed using a polysilicon layer, a tungsten layer, and a titanium or other silicide metal layer separated by a barrier layer, with a tungsten liner between the titanium layer and the barrier layer to reduce interface resistance and maintain low sheet resistance, achieved through Physical Vapor Deposition (PVD) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a titanium silicide metal layer is used between polysilicon and barrier layer, then interface resistance is reduced, but sheet resistance increases
Solution Approach 1:
A tungsten liner layer is introduced as an intermediary between the titanium silicide metal layer and the barrier layer. This liner layer mediates the interaction between titanium and tungsten, preventing titanium from significantly increasing the sheet resistance of the tungsten layer while allowing the titanium to maintain low interface resistance. The tungsten liner acts as a buffer that isolates the detrimental effect of titanium on tungsten grain growth.
Solution Approach 2:
The gate structure employs a composite multi-layer construction consisting of polysilicon, titanium silicide metal layer, tungsten liner layer, barrier layer, and tungsten layer. Each layer contributes specific properties: titanium silicide provides low interface resistance, tungsten liner controls sheet resistance, and barrier layer provides diffusion prevention. The composite structure achieves overall low resistance by combining materials with complementary properties.
2Ease of operation
If control lines extend over significant distances to drive select transistors, then transistor control is achieved, but line resistance increases
Solution Approach 1:
The gate structure changes the electrical parameters (resistance) of the transistor by implementing a multi-layer gate construction with specific material properties. The combination of titanium silicide and tungsten layers with controlled thicknesses optimizes the resistance characteristics, allowing for lower resistance gates that can better drive long control lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces interface resistance while maintaining low sheet resistance, improving the efficiency and performance of transistor gates in nonvolatile memory integrated circuits by minimizing the impact of titanium on tungsten grain size and resistance.
Implementation Method 1
The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed in the same Physical Vapor Deposition (PVD) chamber, for example by sputtering a tungsten target to form tungsten layers
Implementation Method 2
adding nitrogen gas during sputtering to form tungsten nitride
Data Source
AI summary
A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.