Complementary Transistor Harmonic Trap for Linear RF Amplifiers
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Solution Overview
Problem
As wireless devices evolve to handle increasing bandwidth and signal complexity, maintaining linearity and accuracy in amplifier circuits becomes challenging due to signal densification, requiring amplifiers that can efficiently amplify input signals without altering their content.
Innovation Solution
The use of an active device comprising an n-type and a p-type transistor with shared source, coupled by capacitors, which provides high breakdown voltage, memorylessness, and harmonic signal trapping capabilities, distinguishing between even and odd signals generated during Class AB or C operation, and is utilized in conjunction with tuning blocks to achieve linear output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bandwidth and signal complexity are increased, then more data can be transmitted, but linearity and signal accuracy deteriorate
Solution Approach 1:
The amplifier is divided into separate n-type and p-type transistor branches, each handling specific signal components. This segmentation allows independent optimization of each branch for linearity while collectively handling complex broadband signals, resolving the contradiction between high data capacity and signal accuracy
Solution Approach 2:
The patent employs memoryless nonlinear distortion compensation by dynamically adjusting operating parameters of the transistors based on input signal characteristics. This enables the amplifier to maintain linearity across varying bandwidth and signal complexity conditions, preventing linearity degradation as data capacity increases
2Reliability
If power supply voltage is increased to improve breakdown voltage, then device reliability improves, but power consumption increases
Solution Approach 1:
The power supply voltage is segmented and distributed across multiple transistor branches rather than applying full voltage to a single device. This segmentation allows each transistor to operate at lower individual voltages (reducing power consumption) while the series configuration maintains high overall breakdown voltage (improving reliability)
Solution Approach 2:
The patent uses a composite configuration of n-type and p-type transistors with complementary characteristics. This composite structure achieves high breakdown voltage through the series arrangement while the complementary device properties enable efficient power utilization, reducing overall power consumption compared to single-type high-voltage designs
Data Source
Figure 1A~1B
Figure 2A~3B
Figure 4A
AI summary
An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.