Transistor Circuit Impedance Transformation

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Solution Overview

Problem

Existing amplifier devices require very high input impedance, particularly for capacitive sensors, but existing impedance transformation techniques are impractical due to the large silicon area consumption and impractical current requirements for achieving giga-ohm ranges.

Innovation Solution

The use of impedance transformations involving pairs of NMOS and PMOS transistor circuits with different channel width to length ratios and overdrive voltages to achieve high impedance levels, minimizing silicon area usage while maintaining accurate impedance values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a very large resistor is inserted between the input of the amplifier device and a bias point to generate an appropriate operating point, then the input impedance requirement is met, but the silicon area consumption becomes excessive

Engineering Contradiction:
Improveinput impedanceVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the operating parameters of transistor circuits, specifically utilizing sub-threshold gate-source voltages to exponentially increase impedance. By operating transistors in the sub-threshold region where gate-source voltage is below the threshold voltage, the circuit achieves giga-ohm range impedance without requiring large physical resistors, thus resolving the contradiction between high impedance and small silicon area.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If transistor circuits with different W/L ratios are used for impedance transformation, then impedance transformation is achieved, but picoamp-level currents are required making the circuit impractical

Engineering Contradiction:
Improveimpedance transformationVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent modifies the voltage parameter by applying sub-threshold gate-source voltages to the transistor circuits. This parameter change enables the circuits to operate in a regime where impedance is exponentially increased without requiring impractically low picoamp currents, making the impedance transformation practical while maintaining reasonable current consumption levels.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If transistor circuits operate with sub-threshold gate-source voltages, then impedance increases exponentially, but the circuits require precise voltage control

Engineering Contradiction:
Improveimpedance valueVSAvoidvoltage control precision
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs feedback mechanisms through current mirror arrangements where transistor circuits are coupled such that their operation is interdependent. The current mirrors provide automatic regulation and stabilization of the sub-threshold operating points, reducing the need for external precise voltage control while maintaining the exponential impedance increase benefit.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9213350B2Impedance transformation with transistor circuits
Publication Date: 2015.12.15 INFINEON TECHNOLOGIES AG
  • US9213350B2 patent drawing
  • US9213350B2 patent drawing
  • US9213350B2 patent drawing

AI summary

In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.