High Voltage Transistor Impurity Gradient for Low ON-Resistance
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Solution Overview
Problem
Existing semiconductor devices face a trade-off between increasing withstanding voltage and decreasing ON-resistance, with current technologies insufficient in addressing this relationship effectively, particularly in high voltage transistors used for plasma display pixel driving.
Innovation Solution
A semiconductor device configuration with a high voltage transistor structure that includes a semiconductor substrate with specific impurity layers and a conductive layer, where the concentration of impurities in these layers is carefully controlled to minimize ON-resistance while maintaining high withstanding voltage, achieved through a manufacturing method that forms these layers with precise impurity concentration gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the gate electrode and source/drain regions is increased to increase withstanding voltage, then the withstanding voltage is improved, but the ON-resistance increases thereby lowering current performance
Solution Approach 1:
The patent applies local quality by creating impurity layers with different concentrations at different locations within the semiconductor structure. Specifically, high-concentration impurity layers are formed near the source/drain regions to reduce ON-resistance, while the overall channel length is extended to maintain high withstanding voltage. This spatial variation in impurity concentration allows simultaneous optimization of both parameters.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming multiple impurity layers with different concentrations (first impurity layer, second impurity layer with higher concentration, third impurity layer with even higher concentration). This parameter variation allows the structure to achieve low ON-resistance in critical regions while maintaining the extended channel length needed for high withstanding voltage.
2Reliability
If the channel length is extended to increase withstanding voltage, then the withstanding voltage is improved, but the device area increases
Solution Approach 1:
The patent applies the nesting principle by placing multiple impurity layers (first, second, and third impurity layers with increasing concentrations) within each other in the vertical direction. This nested structure allows the channel to be extended in the horizontal direction for high withstanding voltage while utilizing the vertical dimension to maintain compact device area through concentrated impurity regions.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by forming impurity layers at different depths and concentrations. This dimensional change allows the channel length to be extended for high withstanding voltage while keeping the device footprint compact by utilizing the vertical dimension for impurity layer placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ON-resistance while maintaining high withstanding voltage, enabling efficient current flow and stable operation of semiconductor devices, particularly in high voltage applications such as plasma display pixel driving.
Implementation Method 1
a first impurity layer formed over the main surface of the semiconductor substrate, a second impurity layer formed inside the first impurity layer, a pair of third impurity layers formed in the inside of the pair of first impurity layers... The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and fifth impurity layers
Data Source
AI summary
The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.