High and Low Voltage Transistor Integration on Single Substrate
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing multi-functional semiconductor devices that require different process conditions for various generations of transistors, making it difficult to satisfy all required characteristics.
Innovation Solution
A semiconductor device and manufacturing method that include both high voltage and low voltage transistors on a single substrate, with distinct design features such as varying source/drain regions, gate insulating layers, and gate electrodes, allowing for efficient integration of different transistor types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors of various generations with different characteristics are implemented to provide multi-functional semiconductor devices, then the functionality and versatility of the semiconductor device is improved, but the manufacturing complexity increases due to different process conditions required for each transistor type
Solution Approach 1:
The patent applies local quality by implementing different transistor structures in different regions of the semiconductor device. High voltage transistors use thicker gate insulating layers and larger channel widths in specific regions, while low voltage transistors use thinner gate insulating layers in other regions. This allows each region to be optimized for its specific function while using a unified manufacturing process.
Solution Approach 2:
The patent changes physical parameters of the transistor structures to accommodate different functionality requirements. The gate insulating layer thickness is varied (thicker for high voltage, thinner for low voltage), channel widths are adjusted, and doping concentrations are modified. These parameter changes enable multi-functionality while maintaining process compatibility.
2Manufacturing precision
If different process conditions are used for manufacturing transistors of various generations, then the manufacturing precision for each transistor type can be optimized, but the overall manufacturing time and cost increase
Solution Approach 1:
The patent implements a unified manufacturing process that can produce multiple types of transistors (high voltage and low voltage) simultaneously. The process uses common materials and steps, with only minor parameter adjustments needed for different transistor types. This eliminates the need for separate manufacturing lines and reduces overall manufacturing time while maintaining precision for each transistor type.
3Productivity
If transistors with different characteristics are integrated in a single semiconductor device, then the productivity and integration level is improved, but the difficulty of satisfying all required characteristics increases
Solution Approach 1:
The patent segments the semiconductor device into different functional regions, each containing transistors optimized for specific characteristics. High voltage transistors are placed in regions with thicker gate insulating layers, while low voltage transistors are placed in regions with thinner gate insulating layers. This spatial segmentation allows each transistor type to meet its characteristic requirements while being integrated in a single device.
Data Source
AI summary
Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.