High-Voltage Transistor Isolation Edge Implant Parasitic Suppression
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Solution Overview
Problem
High-voltage transistors with shallow trench isolation regions face issues due to parasitic transistors caused by sharp active corners, leading to leakage current and reliability problems, which existing methodologies have not adequately addressed.
Innovation Solution
An isolation edge implant with impurities of a higher concentration than the active region is applied to suppress parasitic transistors, increasing the threshold voltage and disrupting the electric field at the trench edge, thereby eliminating the double hump issue without requiring additional process steps or masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sharp active corners are used at the trenched isolation region edge, then manufacturing precision is improved, but parasitic transistors are formed with lower threshold voltage causing leakage current
Solution Approach 1:
The patent applies different impurity concentrations at different locations: the active region has impurities at a first concentration, while the isolation edge implant applies impurities of the same type at a second concentration that is greater than or equal to the first concentration. This local variation in impurity concentration suppresses the parasitic transistor at the isolation edge while maintaining the intended transistor characteristics in the active region.
Solution Approach 2:
The isolation edge implant is performed before forming the gate electrode, preemptively suppressing the parasitic transistor formation at the isolation region edge. By introducing high concentration impurities at this location beforehand, the patent prevents the parasitic transistor from developing a low threshold voltage that would cause leakage current.
2Stability of the object's composition
If field oxide thinning occurs at corners under transistor gates, then thermal oxide growth is improved, but fringing electric field problems are exacerbated
Solution Approach 1:
The isolation edge implant targets specifically the isolation region edge where the gate oxide extends over the trench isolation region. By applying high concentration impurities locally at this position, the patent counteracts the fringing electric field effect caused by field oxide thinning at corners, without affecting the overall oxide growth characteristics.
3Object-generated harmful factors
If additional edge rounding processes are implemented to suppress parasitic transistors, then parasitic transistor formation is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
The isolation edge implant is combined with the existing implant process flow, utilizing the same implantation equipment and methodology already present in the manufacturing line. By integrating the parasitic transistor suppression function into an existing process step rather than adding a separate edge rounding process, the patent avoids increasing device complexity and manufacturing cost.
Solution Approach 2:
The patent suppresses parasitic transistors by changing the impurity concentration parameter at the isolation edge, using a second concentration that is greater than or equal to the first concentration. This parameter change approach achieves parasitic transistor suppression through material composition modification rather than adding geometric processing steps like edge rounding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents parasitic transistors from activating, improving the reliability and performance of high-voltage transistors by increasing the threshold voltage and eliminating the need for additional edge rounding processes, resulting in a 20% yield improvement without increasing costs or complexity.
Implementation Method 1
applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor
Data Source
AI summary
A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.