Nanostructure Transistor Isolation via Vertical Inner Spacer Profiles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication methods fail to completely remove semiconductor layers during the formation of isolation structures in nanostructure transistors, leading to incomplete isolation and electrical coupling between adjacent transistors.
Innovation Solution
The method involves shaping the sidewalls of inner spacers on the side facing a middle channel structure during the removal of the middle channel structure, ensuring a nearly vertical profile to facilitate complete removal of semiconductor layers and form a reliable isolation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form isolation structures, then the process is simple and fast, but semiconductor layers are not completely removed leading to incomplete isolation
Solution Approach 1:
The method performs preliminary shaping of inner spacer sidewalls to a nearly vertical profile before removing the middle channel structure. This preliminary action ensures that subsequent etching processes can completely remove semiconductor layers down to the substrate, achieving complete isolation without requiring overly complex multi-step fabrication processes.
Solution Approach 2:
The fabrication process is divided into distinct sequential steps: forming inner spacers, shaping their sidewalls to vertical profiles, removing the middle channel structure, and forming the isolation structure. This segmentation allows each step to be optimized independently, ensuring complete layer removal while maintaining process manageability.
2Reliability
If the middle channel structure is removed without shaping inner spacer sidewalls, then the fabrication process is simpler, but semiconductor layers remain causing electrical coupling between transistors
Solution Approach 1:
The inner spacer sidewalls are pre-shaped to a nearly vertical profile using anisotropic etching before the middle channel structure removal. This preliminary action creates optimal conditions for complete semiconductor layer removal, ensuring electrical isolation between transistors while adding only a single etching step to the fabrication process.
Solution Approach 2:
The etching process parameters are changed to achieve anisotropic etching that creates vertical sidewalls on the inner spacers. This parameter change enables the etchant to remove semiconductor layers completely down to the substrate, preventing electrical coupling while maintaining fabrication simplicity.
Data Source
AI summary
A semiconductor device includes a plurality of first channel layers vertically spaced from one another and a plurality of second channel layers vertically spaced form one another. Each of the plurality of first and second channel layers extend along a first lateral direction. The semiconductor device includes an isolation structure disposed between the plurality of first channel layers and the plurality of second channel layers along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a plurality of inner spacers discretely disposed along a first sidewall of the isolation structure that faces toward the first lateral direction, or discretely disposed along a second sidewall of the isolation structure that faces away from the first lateral direction wherein an interface between each of the plurality of inner spacers and the first or second sidewall has a vertical profile.