Transistor Isolation via Stepped Silicon Surfaces
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Solution Overview
Problem
Shallow trench isolation (STI) technology limits the integration density of semiconductor devices due to the limitations in reducing the size of trenches, which in turn affects the circuit area and insulating properties between elements.
Innovation Solution
The approach involves forming transistors on different silicon surfaces using selective epitaxial growth, eliminating the need for STI by creating a silicon layer that insulates the transistors, allowing for a staggered arrangement that reduces the circuit area and enhances electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STI technology is used to isolate transistors, then electrical insulation between elements is achieved, but circuit area cannot be reduced sufficiently due to trench width and depth limitations
Solution Approach 1:
The patent transitions from planar isolation (STI trenches in the same silicon surface) to three-dimensional isolation by forming transistors on different silicon surfaces at different heights. The first transistor is formed on a first silicon surface, while the second transistor is formed on a second silicon surface that is elevated above the first surface, achieving insulation through vertical separation rather than horizontal trench isolation.
Solution Approach 2:
The patent divides the transistor structure into separate vertical segments on different silicon surfaces. By creating distinct height levels for different transistors through selective epitaxial growth, the design segments the circuit layout vertically, allowing transistors to be isolated by their positional difference in the vertical dimension rather than requiring horizontal separation by trenches.
2Area of stationary object
If trench size is reduced to minimize circuit area, then integration density improves, but insulating properties between elements deteriorate
Solution Approach 1:
Instead of relying on reduced horizontal trench dimensions for isolation, the patent achieves insulation by exploiting the vertical dimension. Transistors are positioned at different heights on separate silicon surfaces, and this vertical separation provides sufficient electrical insulation without requiring small trench features, thereby maintaining both small circuit area and strong insulating properties.
3Area of stationary object
If elements are arranged closer together to reduce circuit area, then integration density increases, but manufacturing precision requirements increase due to tighter spacing
Solution Approach 1:
By arranging transistors on different vertical levels rather than in tight horizontal proximity, the patent reduces the precision requirements for lateral alignment and spacing. The vertical separation through different silicon surfaces provides inherent isolation that relaxes the manufacturing precision demands compared to planar arrangements with minimal spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for a significant reduction in circuit area, achieving about two-thirds reduction compared to STI-based designs, while maintaining excellent electrical insulating properties and enabling high-density integration of memory cells.
Implementation Method 1
a silicon layer formed adjacent to the first transistor on a surface of the silicon substrate by selective epitaxial growth
Data Source
AI summary
According to the present invention, it is possible to isolate elements from each other without formation of STI and integrate the elements at a high density. A step is formed on a surface of a silicon substrate so as to provide different surfaces. Transistors are formed on the respective different surfaces. The transistors are insulated from each other by a silicon layer and an insulating sidewall. Since no STI is formed between the transistors, it is possible to integrate the transistors at a high density.