Transistor Isolation Void Filling via Plasma Treatment
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Solution Overview
Problem
As semiconductor devices become highly integrated, the decreasing size of MOS transistors poses a challenge in ensuring reliable operation, particularly due to the need for precise formation of transistors with small channel lengths and effective isolation to prevent defects.
Innovation Solution
A method involving the formation of trenches in a substrate, followed by the creation of active patterns and isolation layers with voids, which are then filled using a plasma treatment process to oxidize or nitrify the insulation layers, allowing for the formation of recesses and gate electrodes while preventing material accumulation in voids and enhancing transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of MOS transistors is decreased to achieve high integration, then the integration density is improved, but the reliability of transistor operation deteriorates due to smaller channel lengths and potential defects
Solution Approach 1:
The patent performs preliminary actions by forming isolation layers with intentional voids before transistor fabrication, then systematically removing these voids through plasma treatment and oxidation/nitridation processes. This preliminary void removal prevents potential defects that would compromise transistor reliability at scaled dimensions.
Solution Approach 2:
The patent changes the chemical and physical parameters of the isolation layer by transforming it from a solid structure to one containing controlled voids, then systematically removing these voids through plasma treatment and oxidation/nitridation. This parameter transformation ensures complete void elimination while maintaining the isolation layer's structural integrity for reliable transistor operation.
2Reliability
If isolation layers are formed to prevent defects and ensure reliable operation, then the transistor reliability is improved, but the process complexity and manufacturing steps increase
Solution Approach 1:
The patent merges multiple functions into the isolation layer: it provides electrical isolation between transistors, serves as a structural support during fabrication, and contains intentional voids that are subsequently removed to prevent defects. The plasma treatment and oxidation/nitridation processes also serve dual purposes of void removal and photoresist removal, reducing overall process complexity.
Solution Approach 2:
The isolation layer performs multiple functions: electrical isolation, structural support, and defect prevention through controlled void formation and removal. The plasma treatment process simultaneously removes both voids and photoresist patterns, demonstrating multi-functionality that reduces the number of separate manufacturing steps required.
3Ease of manufacture
If voids are present in isolation layers, then the manufacturing process is simplified, but defects may occur and transistor reliability deteriorates
Solution Approach 1:
The patent performs preliminary void removal through plasma treatment and oxidation/nitridation before completing transistor fabrication. This preliminary action eliminates potential defect sources while maintaining the manufacturing simplicity of forming isolation layers with voids, ensuring subsequent transistor operation reliability.
Solution Approach 2:
The patent changes the physical state of the isolation layer by transforming solid regions into controlled voids, then systematically removing these voids through plasma treatment and oxidation/nitridation. This parameter transformation maintains ease of manufacture while eliminating reliability concerns associated with voids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and improves the reliability of transistors by ensuring proper filling of voids within the isolation layers, thereby enhancing the integration and performance of semiconductor devices while minimizing production costs and time.
Implementation Method 1
A plasma treatment process is performed, removing the photoresist pattern and filling the void
Implementation Method 2
The second insulation layer pattern may be oxidized, filling the void
Implementation Method 3
The first insulation layer pattern may be nitrified, filling the void
Data Source
AI summary
A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.