Transistor Jog Isolation Structure for Epitaxial Silicon Protection
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Solution Overview
Problem
The existing photolithographic patterning and etching processes for semiconductor wafer fabrication face challenges in efficiently isolating adjacent transistors, particularly in jog regions where high and low current density regions are integrated, and in preventing damage to epitaxial silicon structures during transistor isolation processes.
Innovation Solution
A continuous poly on diffusion edge (CPODE) structure is formed by etching semiconducting fins and creating a trench in the substrate, which is then filled with dielectric material to provide electrical isolation between neighboring active device regions, such as transistors, especially in jog regions where semiconducting fins of different widths are joined.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional photolithographic patterning and etching processes are used to isolate adjacent transistors, then transistor isolation can be achieved, but damage to epitaxial silicon structures occurs and processing complexity increases
Solution Approach 1:
The CPODE structure is formed before final transistor fabrication to pre-establish isolation regions. By creating the isolation structure in advance using selective etching of sacrificial nanosheets, the patent prevents subsequent processing steps from damaging epitaxial silicon structures, as the isolation regions are already defined and protected
Solution Approach 2:
Sacrificial nanosheets are introduced as intermediary structures that facilitate the formation of CPODE isolation regions. These temporary structures enable selective etching to create isolation trenches without directly contacting or damaging the epitaxial silicon structures, serving as a protective mediator during the isolation process
2Adaptability or versatility
If separate manufacturing steps are used to integrate wide and narrow nanosheets, then current density requirements can be met, but manufacturing complexity and processing costs increase
Solution Approach 1:
The patent merges the fabrication of wide and narrow nanosheets into a single continuous structure. By forming one unified nanosheet layer that spans both high and low current density regions, the process eliminates the need for separate manufacturing steps, reducing complexity while maintaining the ability to meet different current density requirements through the continuous structure
Solution Approach 2:
The continuous nanosheet structure incorporates local variations in width to satisfy different current density requirements in different regions. The nanosheet maintains its continuity while exhibiting local quality differences - wider in high current density regions and narrower in low current density regions - allowing a single structure to fulfill multiple functional requirements
Data Source
AI summary
Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.