Transistors With Laterally Extended Active Regions
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Solution Overview
Problem
There is a need for techniques to reduce the size of transistors while maintaining a desirable effective channel width, as reducing the two-dimensional size of transistors can lead to decreased current drivability and conflict with high integration requirements.
Innovation Solution
The approach involves forming a semiconductor device with upper and lower active regions of different widths, where an insulated gate electrode extends through both regions, with the lower gate electrode being wider than the upper gate electrode, and the isolation regions are designed to define these active regions, allowing for a laterally extended active region and increased effective channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the two-dimensional size of transistors is reduced to increase integration density, then the area occupied by the transistor is reduced, but the effective channel width is decreased leading to reduced current drivability
Solution Approach 1:
The patent extends the active region laterally in the vertical dimension (depth) to compensate for the reduction in horizontal channel width. By creating a deeper active region with increased vertical extent, the effective channel width is maintained through the additional vertical channel path, allowing the transistor to achieve smaller footprint while preserving current drivability
Solution Approach 2:
The patent nests the lower active region within the vertical structure above it, creating a stacked configuration where the lower active region is positioned beneath the upper active region. This nested arrangement allows the transistor to utilize vertical space efficiently, maintaining effective channel width through the lower region while occupying less horizontal area
2Speed
If the channel length is reduced to increase drive current and response speed, then the drive current and response speed are improved, but punch-through problems occur
Solution Approach 1:
The patent compensates for reduced channel length by extending the channel in the vertical dimension. The deeper active region provides additional vertical channel length, maintaining the effective channel length needed to prevent punch-through while allowing shorter horizontal channel dimensions for faster response
3Area of stationary object
If the active region size is reduced to minimize transistor footprint, then the transistor area is reduced, but the effective channel width is decreased
Solution Approach 1:
The patent compensates for reduced horizontal active region dimensions by increasing the vertical extent of the active region. The deeper vertical channel path provides additional effective channel width, allowing the active region footprint to be minimized while maintaining adequate current flow capacity
Data Source
AI summary
A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.