Multi-Finger Transistor Layout with 45-Degree Gate Orientation
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Solution Overview
Problem
The integration of p-channel and n-channel transistors on the same chip in semiconductor devices faces challenges in minimizing on-resistance due to the ineffective regions created when their channel directions intersect at an angle, which hinders the improvement of carrier mobility and performance.
Innovation Solution
The transistors are arranged with their gates in a multi-finger structure, where the p-channel transistor gates are oriented at 45 degrees relative to the n-channel transistor gates, with a specific pitch-to-gate-width ratio optimized to minimize ineffective regions and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel directions of n-channel and p-channel transistors are arranged at 45 degrees to improve carrier mobility, then carrier mobility is improved, but ineffective regions are generated that increase on-resistance
Solution Approach 1:
The patent applies local quality by configuring the n-channel transistor with channel direction <110> and the p-channel transistor with channel direction <100>, creating different crystal orientations in different regions. This allows each transistor type to have its channel direction optimized for maximum carrier mobility while the overall layout minimizes ineffective regions through specific pitch-to-gate-width ratio control.
Solution Approach 2:
The patent changes the geometric parameters of the transistor layout by controlling the pitch-to-gate-width ratio to be 0.05 or less. This parameter optimization ensures that when transistors are arranged with 45-degree angle between channel directions, the ineffective regions are minimized, thereby reducing on-resistance while maintaining high carrier mobility.
2Object-affected harmful factors
If the pitch-to-gate-width ratio is reduced to minimize ineffective regions, then on-resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes a specific design criterion that the pitch-to-gate-width ratio should be 0.05 or less. This quantified parameter provides clear manufacturing guidance and control standards, making it easier to achieve the desired layout precision during fabrication while minimizing ineffective regions and reducing on-resistance.
3Object-affected harmful factors
If multi-finger structure is used to increase gate width and reduce on-resistance, then transistor performance is improved, but chip area occupation increases
Solution Approach 1:
The patent utilizes the angular dimension by arranging n-channel and p-channel transistor channels at 45 degrees to each other. This dimensional approach allows more efficient packing of multi-finger structures, reducing the chip area occupied while maintaining the total gate width needed to minimize on-resistance.
Solution Approach 2:
By assigning different channel directions (<110> for n-channel, <100> for p-channel) to different transistor types, the patent optimizes each region's configuration to minimize ineffective areas, thereby reducing the total chip area required for the multi-finger transistor structure while maintaining low on-resistance.
Data Source
AI summary
A semiconductor device for improving performance of a p-channel transistor and an n-channel transistor having multi-finger structures. Gates of the n-channel transistor are arranged so that their gate width direction is parallel to one side of a first region. Gates of the p-channel transistor are arranged so that their gate width direction extends at an angle of 45 degrees with respect to one side of a second region. The ratio of a maximum gate width of the p-channel transistor arranged in the second region to the pitch between the gates of the p-channel transistor is set in accordance with the ratio of the area of an ineffective region to the area of the second region.