Semiconductor Transistor Layout With Stepped Source/Drain Reliability
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Solution Overview
Problem
Existing semiconductor devices face reliability issues due to adverse effects during the manufacturing process of transistors in peripheral circuit regions, especially when the number of word lines is increased to improve integration density in three-dimensionally arranged memory cells.
Innovation Solution
The semiconductor device incorporates a design with first and second transistors in different regions, each with specific gate dielectric films, gate electrodes, and insulating spacers. The transistors have source/drain regions with substrate step portions at different vertical levels, and the gate dielectric films have varying thicknesses and widths to enhance reliability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to improve integration density, then integration density is improved, but reliability deteriorates due to adverse effects during transistor manufacturing
Solution Approach 1:
The patent applies local quality by creating different gate dielectric film thicknesses in different regions. The first gate dielectric film has a first thickness in a first region, while the same film has a second thickness greater than the first thickness in a second region. This allows transistors in different regions to have optimized characteristics for their specific functions, improving reliability without sacrificing integration density.
Solution Approach 2:
The gate dielectric film is segmented into multiple thickness regions within the same continuous film structure. This segmentation allows different portions of the transistor to experience different electric field distributions and manufacturing conditions, protecting against adverse effects while maintaining high integration density through the continuous film architecture.
2Reliability
If gate dielectric film thickness is increased to protect transistor operations, then reliability is improved, but device area increases
Solution Approach 1:
Instead of uniformly increasing gate dielectric film thickness across the entire device, the patent applies local quality by having the film exhibit a first thickness in a first region and a second greater thickness only in a second region. This localized approach protects transistor operations in critical areas while minimizing the overall area increase.
Solution Approach 2:
The patent resolves the area-reliability contradiction by transitioning to a three-dimensional structure where gate dielectric film thickness varies in the vertical dimension across different horizontal regions. This allows reliability improvement through increased thickness in specific areas without proportionally increasing the planar device area.
Data Source
AI summary
A semiconductor device includes a first gate dielectric film on a first channel top surface of a substrate, wherein the first channel top surface is in a first region of the substrate, a first gate electrode on the first gate dielectric film, first offset insulating spacers respectively on opposing sidewalls of each of the first gate dielectric film and the first gate electrode, first main insulating spacers respectively on the opposing sidewalls of the first gate electrode, wherein the first offset insulating spacers are between the first main insulating spacers, and a pair of first source/drain regions in the substrate on opposing sides of the first gate electrode, wherein a top surface of each of the pair of first source/drain regions includes at least two first-voltage substrate step portions having respective surfaces that are lower than the first channel top surface of the substrate in a vertical direction.