Transistor-Level Synthesis for Integrated Circuit Area Reduction
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Solution Overview
Problem
Integrated circuit design, particularly for specialized circuits like ASICs and SoCs, faces challenges in efficiently mapping logic gates to standard cells, leading to increased transistor count and circuit area, with existing methods being inefficient in optimizing for both area and signal delay.
Innovation Solution
The approach involves transistor-level synthesis using novel optimization algorithms to generate single-stage and multi-stage transistor networks directly from Boolean functions, minimizing the number of literals and transistors through factored form optimization, and performing technology mapping to reduce circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cell library approach is used for technology mapping, then design process is simplified and cells are pre-characterized, but the number of transistors and circuit area increase
Solution Approach 1:
The patent segments the technology mapping process into two distinct phases: (1) generating an optimized transistor-level netlist using novel algorithms that minimize literal count, and (2) performing standard cell mapping on this optimized netlist. This segmentation allows the transistor minimization to be decoupled from the standard cell mapping constraints, enabling fewer transistors while maintaining ease of manufacture through the use of standard cells.
Solution Approach 2:
The patent applies preliminary optimization actions by generating the transistor-level netlist with minimized literal count before performing the standard cell mapping. The novel algorithms (such as the two-phase algorithm and logic cone rewriting) perform preliminary minimization of the Boolean functions representing each logic cone, so that when standard cell mapping is applied, it operates on an already-optimized structure that requires fewer transistors.
2Ease of operation
If conventional standard cell mapping is used, then placement and routing is straightforward, but circuit area and power consumption increase
Solution Approach 1:
The patent performs preliminary minimization of the transistor-level netlist before standard cell mapping. By applying novel algorithms that minimize the literal count of Boolean functions representing logic cones, the circuit is optimized in advance. This preliminary action ensures that when standard cell mapping and placement are performed, they operate on a minimized structure, reducing the final circuit area while maintaining ease of operation.
Solution Approach 2:
The patent changes the optimization parameter from traditional area-based or delay-based metrics to literal count minimization at the transistor level. By focusing on minimizing the number of literals in the factored form of Boolean functions, the patent indirectly optimizes the number of transistors and circuit area, while the subsequent standard cell mapping maintains ease of operation.
3Ease of manufacture
If more transistors are used in standard cell implementation, then logic functions can be more easily implemented, but power consumption increases
Solution Approach 1:
The patent changes the optimization focus to minimizing the literal count of Boolean functions at the transistor level. By representing each logic cone's function in factored form and minimizing literals, the patent reduces the number of transistors required. This parameter change directly addresses power consumption since fewer transistors mean lower dynamic power, while still implementing the required logic functions through the systematic two-phase approach.
4Extent of automation
If existing optimization algorithms are used for logic synthesis, then design automation is provided, but literal count and circuit area are not minimized
Solution Approach 1:
The patent replaces traditional mechanical logic synthesis approaches with novel algorithms that specifically target literal count minimization. The two-phase algorithm, logic cone rewriting, and factored form optimization replace conventional synthesis methods, providing design automation while explicitly minimizing literal count as the optimization criterion, thereby reducing circuit area.
Data Source
AI summary
The technology involves transistor-level synthesis for integrated circuit design and fabrication. According to one aspect, a computer-implemented method performs transistor-level synthesis for an integrated circuit element. This includes generating single-stage transistor networks from Boolean functions, in which each single-stage transistor network is composed of a pulldown network and a pullup network. The single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals. Technology mapping can then be performed based on the factored form literals to generate a circuit design.