3D Transistor Liner Structure for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling and maintaining reliability due to short channel effects and limited current control ability, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a semiconductor liner film with varying widths and an epitaxial insulating liner extending along the sidewalls of source/drain patterns, along with a specific gate structure design to enhance control and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-gate transistor with three-dimensional channel is used to improve current control ability, then current control is improved, but device complexity increases
Solution Approach 1:
The device is divided into multiple functional segments: lower pattern (fin structure), semiconductor liner film, epitaxial insulating liner, semiconductor filling film, and gate structure. Each segment performs a specific function, allowing complex 3D channel control to be achieved through coordinated simple structures rather than a monolithic complex design
Solution Approach 2:
The patent employs nested structures where the epitaxial insulating liner is positioned within the semiconductor liner film, which is itself within the source/drain pattern. This nested arrangement enables multiple functions (insulation, structural support, electrical connection) to be integrated in a compact hierarchy, improving current control without proportionally increasing device complexity
2Productivity
If the channel length is reduced to increase device density, then productivity is improved, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel control to three-dimensional channel control by introducing vertical structures (lower pattern fins, epitaxial insulating liner on sidewalls). This dimensional change enables effective channel control in the vertical dimension, allowing shorter horizontal channel lengths to be used while maintaining electrostatic control and suppressing short channel effects
Solution Approach 2:
The epitaxial insulating liner is selectively positioned on the sidewalls of the semiconductor liner film in the channel region, providing localized electrostatic control exactly where needed. This localized approach enhances short channel effect suppression at the critical channel interface without requiring uniform structural modifications throughout the entire device, thereby maintaining high device density
3Reliability
If the gate length is increased to suppress short channel effects, then reliability is improved, but device density decreases
Solution Approach 1:
By introducing vertical control elements (epitaxial insulating liner on sidewalls, lower pattern fins) that extend into the third dimension, the patent achieves effective channel control without increasing the horizontal gate length. The vertical structures provide additional electrostatic control that compensates for shorter channel lengths, enabling high device density while maintaining reliability
4Ease of manufacture
If a simple planar transistor structure is used to reduce device complexity, then ease of manufacture is improved, but current control ability worsens
Solution Approach 1:
The device is divided into multiple sequentially formed segments (lower pattern, liner film, insulating liner, filling film, gate structure), where each segment can be manufactured using standard semiconductor processing techniques. This segmentation allows complex 3D functionality to be achieved through a series of relatively simple, well-established manufacturing steps rather than requiring complex single-step processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves element performance and reliability by effectively suppressing short channel effects and enhancing current control in multi-gate transistors.
Implementation Method 1
an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film
Data Source
AI summary
A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of a sidewall of the first portion of the semiconductor liner film.