Transistor Local Interconnect Layout for Compact Cross-Coupling
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Solution Overview
Problem
As semiconductor devices shrink to the 20 nm node, traditional methods for cross-coupling transistors become inefficient, leading to increased area usage and reduced functionality due to lithographic limitations and reliance on standard metal layers.
Innovation Solution
The use of CA and CB layers as local interconnects, electrically connected to the sources, drains, and gates of transistors, allows for cross-coupling without relying on standard metal layers, thereby conserving semiconductor device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cross-coupling methods using standard metal layers are used, then transistor connectivity is achieved, but semiconductor device area increases
Solution Approach 1:
The patent introduces a new interconnect dimension by forming local interconnects within the active transistor layer using doped regions and isolation structures, rather than relying solely on planar metal layers. This vertical integration of interconnect functions into the transistor fabrication process reduces the need for additional lateral metal routing, thereby conserving device area while maintaining connectivity.
2Reliability
If standard metal layers are used for interconnects, then electrical connectivity is established, but manufacturing complexity increases
Solution Approach 1:
The patent merges the interconnect formation process with the transistor fabrication process by using the same doped region formation, isolation layer deposition, and patterning steps for both transistor gates/sources/drains and local interconnects. This integration eliminates separate interconnect fabrication steps, reducing overall manufacturing complexity while ensuring reliable electrical connectivity through the unified process flow.
3Length of moving object
If lithographic scaling is applied to reduce device size, then feature size decreases, but standard cell library device scaling is limited
Solution Approach 1:
The patent applies local quality by creating region-specific doped areas that serve dual purposes: forming transistor terminals in some locations and creating local interconnects in others. This localized differentiation within the same fabrication layer allows standard cell library devices to scale effectively with lithography while maintaining both transistor functionality and interconnect capability, overcoming the limitations of uniform scaling approaches.
Data Source
AI summary
A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer