Transistor Material Composition for Low-Temperature Fabrication
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Solution Overview
Problem
Current transistor fabrication methods face challenges in achieving low-temperature processing (below 500°C) with a low thermal budget, which limits deposition temperatures and times, and can result in adverse effects such as melting or poor adhesion of deposited layers to substrates, especially when using plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD) techniques.
Innovation Solution
The method involves forming transistors with a structure where an upper material and a lower material, both amorphous to up to 20% crystalline, are annealed to become entirely crystalline, with the upper material containing 1-10 atomic percent elemental-form H and 0-0.1 total atomic percent noble elements, and the lower material containing 0-1 atomic percent elemental-form H and 0.1-10 total atomic percent noble elements, to improve adhesion and structural properties while reducing thermal budget requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If low-temperature processing (below 500°C) is used, then thermal budget constraints are satisfied, but adhesion and structural properties of deposited layers deteriorate
Solution Approach 1:
The patent changes the chemical composition parameters of the deposited layers by incorporating specific ratios of silicon, germanium, and tin elements, along with controlled amounts of hydrogen and noble elements. This compositional parameter change enables the material to maintain structural integrity and adhesion properties at lower processing temperatures below 500°C, resolving the contradiction between temperature reduction and property maintenance.
Solution Approach 2:
The patent employs composite material structures with multiple layers containing different elemental compositions (silicon-germanium-tin alloys with hydrogen and noble element additions). These composite structures provide improved adhesion between layers and enhanced structural stability at low temperatures, allowing the system to achieve both low thermal budget and high reliability simultaneously.
2Use of energy by stationary object
If deposition temperature is limited, then thermal budget is reduced, but void formation increases and manufacturing precision deteriorates
Solution Approach 1:
The patent modifies deposition parameters including temperature, pressure, and gas flow ratios during PECVD processing to optimize film quality. By carefully controlling these parameters within the low-temperature regime, the method achieves complete layer coverage with minimal void formation while maintaining the thermal budget constraint.
Solution Approach 2:
The patent introduces hydrogen and noble elements as intermediary substances during the deposition process. These intermediaries facilitate better atomic arrangement and bonding in the deposited layers, reducing void formation and improving manufacturing precision even when deposition is performed at limited temperatures that conserve thermal budget.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistors at lower temperatures with improved adhesion and structural properties, reducing void formation and facilitating low-doped channel regions, thus addressing thermal budget constraints and enhancing the reliability of integrated circuitry.
Implementation Method 1
The upper material and the lower material are annealed such that the upper material and the lower material are entirely crystalline
Implementation Method 2
plasma enhanced chemical vapor deposition (PECVD)
Implementation Method 3
physical vapor deposition (PVD) techniques
Data Source
AI summary
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.