Transistor Model Gate CD Offset for Simulation Accuracy
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Solution Overview
Problem
Transistor models, such as MOSFET models, face inaccuracies in circuit simulation due to differences in gate lengths between I-V and C-V test structures caused by process variations, leading to discrepancies between simulated and measured circuit data.
Innovation Solution
A method to adjust the transistor model by determining a gate CD offset using source off-current measurements from both I-V and C-V test structures, allowing for compensation of gate length differences, thereby enhancing simulation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistor model parameters are extracted from I-V and C-V measurements using standard fabrication processes, then the manufacturing process is simple and fast, but process variations cause gate length differences between test structures leading to inaccurate circuit simulation results
Solution Approach 1:
The patent applies preliminary action by determining a gate CD offset value before circuit simulation. The offset is calculated from test structure measurements and then applied to adjust the transistor model parameters in advance, ensuring accurate simulation results without modifying the fabrication process. This pre-adjustment approach resolves the contradiction by maintaining simple manufacturing while achieving precise gate length consistency through computational correction.
2Measurement precision
If the transistor model uses gate lengths from different test structures without adjustment, then the model extraction process is straightforward, but circuit simulation accuracy deteriorates due to gate length variations from process variations
Solution Approach 1:
The patent introduces a gate CD offset value as an intermediary parameter that mediates between the measured gate lengths from different test structures and the required accurate gate length for circuit simulation. This offset acts as a correction factor that bridges the gap between straightforward model extraction and high simulation accuracy, resolving the contradiction by adding a computational intermediary step that maintains ease of manufacture while achieving measurement precision.
3Manufacturing precision
If process variations such as etchant distribution and photolithographic diffraction are controlled to minimize gate length variations, then gate length consistency improves, but manufacturing process complexity and cost increase
Solution Approach 1:
The patent replaces mechanical/process control approaches with a computational method. Instead of modifying fabrication processes to control gate length variations, the invention uses a gate CD offset calculation that computationally compensates for variations. This substitution resolves the contradiction by replacing complex process control mechanisms with a simpler mathematical correction applied during model extraction.
Data Source
AI summary
According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.