Transistor Non-Circular Via Orientation for Inductance and Electromigration
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Solution Overview
Problem
Existing transistor layouts face a tradeoff between minimizing common-node inductance and die size, with 'slot via' layouts reducing inductance but increasing die size, and 'end via' layouts reducing die size but degrading power gain due to higher common-node inductance.
Innovation Solution
A transistor layout featuring non-circular via connections in two orientations, where the major axis of the via connection on the input side is oriented perpendicular to the gate to minimize common-mode inductance, and on the output side is oriented parallel to the gate to mitigate electromigration constraints, allowing for reduced die size and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If 'slot via' layouts are used, then common-node inductance is reduced, but die size increases
Solution Approach 1:
The patent applies local quality by making the via connections non-circular with different orientations at different locations. The input-side via has its major axis perpendicular to the gate, while the output-side via has its major axis parallel to the gate. This localized differentiation optimizes each via's function: the input via minimizes common-mode inductance while the output via reduces electromigration, achieving both goals without increasing die size.
Solution Approach 2:
The patent employs asymmetry by using non-circular via connections with different orientations rather than symmetric circular vias. The first via connection has a different orientation (perpendicular to gate) compared to the second via connection (parallel to gate), creating an asymmetric layout that simultaneously addresses both inductance and electromigration issues.
2Area of stationary object
If 'end via' layouts are used, then die size is reduced, but power gain degrades due to higher common-node inductance
Solution Approach 1:
The patent uses local quality by positioning via connections at specific locations (input and output sides) with different orientations tailored to each location's requirements. This localized optimization allows the via connections to minimize inductance where needed while maintaining compact die size, avoiding the inductance penalty of traditional end via layouts.
Solution Approach 2:
The patent changes the geometric parameters of the via connections by using non-circular shapes with specific orientations rather than circular vias. The major and minor axes of the elliptical via connections are oriented differently at the input and output sides, changing the electrical characteristics to reduce both common-node inductance and electromigration effects.
3Object-affected harmful factors
If non-circular via connections with optimized orientation are used, then common-node inductance is reduced and die size is minimized, but electromigration constraints arise
Solution Approach 1:
The patent applies local quality by using different via orientations at different locations: the input-side via has its major axis perpendicular to the gate to minimize inductance, while the output-side via has its major axis parallel to the gate to reduce electromigration. This localized differentiation allows each via to be optimized for its specific functional requirement.
Solution Approach 2:
The patent employs asymmetry by using non-circular via connections with different orientations at the input and output sides. The asymmetric orientation (perpendicular vs. parallel to gate) addresses the conflicting requirements of inductance minimization and electromigration resistance at different locations in the device.
Data Source
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AI summary
A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.