Semiconductor Transistor Offset Layout for Breakdown Voltage and ON Current
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Solution Overview
Problem
Existing semiconductor devices face reliability and performance issues due to unequal offset lengths in transistors with different operation voltages, leading to compromised ON current and transistor characteristics.
Innovation Solution
A semiconductor device design where transistors with different operation voltages have offset lengths tailored to their specific requirements, with longer offset lengths for high-voltage transistors and shorter lengths for low-voltage transistors, ensuring optimal breakdown voltage and reliability while maintaining drivability and reducing the layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the offset length is increased to improve breakdown voltage and reliability, then reliability improves, but the ON current decreases and transistor characteristics deteriorate
Solution Approach 1:
The patent applies different offset lengths to different transistors based on their specific voltage requirements. High-voltage transistors (e.g., pixel selection transistors) have longer offset lengths to ensure breakdown voltage, while low-voltage transistors (e.g., drive transistors) have shorter offset lengths to maintain high ON current. This localized differentiation resolves the contradiction by matching offset length to functional requirements.
Solution Approach 2:
The patent changes the offset length parameter according to the operation voltage of each transistor. By adjusting this geometric parameter based on voltage requirements, the patent optimizes both reliability (for high-voltage devices) and drivability (for low-voltage devices), resolving the trade-off between breakdown voltage and ON current.
2Ease of manufacture
If the offset length is set uniformly for all transistors, then manufacturing is simplified, but reliability and characteristics cannot be optimized for different voltage requirements
Solution Approach 1:
Instead of uniform offset lengths, the patent implements local quality by assigning different offset lengths to transistors in different circuit regions based on their voltage requirements. This allows manufacturing to remain relatively simple while achieving optimized reliability for each transistor type.
Solution Approach 2:
The patent segments the transistor population into groups based on their voltage requirements (high-voltage pixel selection transistors vs. low-voltage drive transistors). Each segment receives an appropriately optimized offset length, resolving the contradiction between manufacturing simplicity and performance optimization.
3Reliability
If the offset length is increased for high-voltage transistors, then breakdown voltage improves, but the layout area increases
Solution Approach 1:
The patent applies longer offset lengths only where high breakdown voltage is required (pixel selection transistors), while using shorter offset lengths for transistors where high ON current is more critical (drive transistors). This localized approach optimizes reliability without unnecessarily increasing overall layout area.
Solution Approach 2:
The patent changes the offset length parameter selectively based on transistor function and voltage requirements. By adjusting this parameter locally rather than globally, the patent achieves necessary breakdown voltage protection while minimizing the impact on total layout area.
Data Source
AI summary
A semiconductor device including first and second transistors is provided. The first transistor includes first and second regions each being arranged between corresponding one of diffusion regions and a channel region and having a lower concentration than the diffusion regions, and a first length of the first region is longer than a length of the second region. The second transistor includes third and fourth regions each being arranged between corresponding one of diffusion regions and a channel region and having a lower concentration than the diffusion regions, and a third length of the third region is longer than a length of the fourth region. A depth of the first region is equal to a depth of the third region, the third length is longer than the first length, and a higher voltage than the first transistor is applied to the second transistor.