Transistor-Based OTP NVM With Redundancy and Majority Voting
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Solution Overview
Problem
Conventional one-time programmable (OTP) memories, particularly those implemented with fuse arrays, lack the ability to be erased once programmed, leading to inefficiencies in data storage and potential fabrication limitations due to the physical size of fuses, which can hinder integration in certain fabrication node technologies.
Innovation Solution
Implementing an OTP array using transistor-based memory cells that prevent erase operations by design, utilizing a unique voltage biasing scheme for reading, writing, and preventing erasure, and employing redundancy and majority voting to ensure reliable data storage despite fabrication defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fuse array is used to implement OTP memory, then data immutability is achieved, but the physical size of fuses hinders integration in certain fabrication node technologies
Solution Approach 1:
The patent uses transistor-based memory cells as copies of conventional OTP implementations, allowing the same OTP functionality to be achieved with a different physical substrate that is compatible with modern fabrication nodes. The transistor cells replicate the one-time programmable behavior through voltage biasing schemes rather than using physical fuses.
Solution Approach 2:
The invention changes the fundamental physical parameter from fuse resistance to transistor threshold voltage. By programming the transistor threshold voltage through charge trapping or interface state modification, the memory achieves OTP functionality with parameters that can be controlled and measured in modern CMOS fabrication processes.
2Ease of manufacture
If transistor-based memory cells are used instead of fuse arrays, then integration in various fabrication node technologies is enabled, but the ability to prevent erase operations by design must be implemented through complex voltage biasing schemes
Solution Approach 1:
The memory array is segmented into OTP and non-OTP portions with physically separated word lines. This segmentation allows different voltage biasing schemes to be applied to different regions, simplifying the overall design by isolating the complex OTP protection logic to specific circuit blocks rather than requiring system-wide complexity.
Solution Approach 2:
The patent introduces an intermediary voltage blocking mechanism where the word line structure itself acts as a mediator that prevents negative voltage application to OTP cells. This intermediary structure provides passive protection without requiring active control logic, reducing the overall system complexity.
3Reliability
If redundancy and majority voting are implemented, then defect tolerance and reliability are enhanced, but the memory cell count and area increase
Solution Approach 1:
The patent merges the redundancy mechanism with the standard memory array structure by using identical transistor-based cells for both primary and redundant storage. The same cell design and readout circuitry are used, allowing redundancy to be implemented without adding separate specialized structures, thus minimizing area overhead.
Data Source
AI summary
In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.