Transistor Oxide Thickness Control via SiGe Recessing
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Solution Overview
Problem
Conventional transistor fabrication methods face challenges in balancing oxide integrity and poly depletion, leading to issues like punchthrough and leakage due to excessive doping, and struggle with controlling Short Channel Effects and dopant diffusion.
Innovation Solution
A method involving the formation of a gate structure with a protective cap, followed by selective etching and implantation of silicon germanium material with boron doping to create compressive strain and reduce threading dislocation defects, while decoupling the implantation of the poly gate structure from the source/drain regions to optimize oxide thickness and minimize leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If heavy doping is performed concurrently with source/drain formation to avoid poly depletion, then oxide thickness can be kept small, but source/drain regions experience overrun of extension regions leading to punchthrough and leakage
Solution Approach 1:
The patent segments the doping process into two distinct stages: first forming extension regions with moderate doping, then performing heavy doping of source/drain regions after recess formation. This temporal and spatial segmentation allows each region to receive appropriate doping levels without contamination, resolving the contradiction between achieving thin oxide and preventing leakage.
Solution Approach 2:
The extension regions are formed in advance with moderate doping before the heavy source/drain doping occurs. This preliminary action establishes a protective barrier that prevents subsequent heavy dopants from overrunning into the channel, while still allowing the oxide to be thin for optimal device performance.
2Manufacturing precision
If Solid Phase Epitaxial Regrowth is used to achieve abrupt junction profiles and suppress dopant diffusion, then Short Channel Effects are controlled, but lateral amorphisation and End of Range defects increase integration complexity
Solution Approach 1:
The patent extracts and removes the problematic amorphous layer formed during ion implantation through selective recess etching. By removing this layer before epitaxial regrowth, the process avoids the integration issues of lateral amorphisation and EOR defects while still achieving abrupt junction profiles through the subsequent controlled epitaxial growth.
Solution Approach 2:
The patent changes the physical state of the damaged silicon layer from amorphous to crystalline through controlled epitaxial regrowth. This parameter change eliminates the harmful effects of lateral amorphisation while preserving the benefits of abrupt junction formation, simplifying the overall integration process.
3Reliability
If decoupling of implantation of poly gate structure from source/drain regions is implemented, then oxide integrity and poly depletion are optimized, but additional process steps are required
Solution Approach 1:
The patent merges the formation of the protective cap over the gate with the subsequent recess formation and doping processes. The cap serves dual purposes: protecting the gate during heavy doping while defining the recess geometry. This merging reduces the net increase in process steps despite the decoupling of gate and source/drain implantation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor mobility and reduces defects associated with conventional strained silicon device solutions, achieving optimal oxide thickness and current flow without compromising gate integrity, resulting in enhanced performance and reduced leakage.
Implementation Method 1
implantation of silicon germanium material with boron doping to create compressive strain
Implementation Method 2
A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions
Implementation Method 3
the recesses are filled with silicon germanium via a selective epitaxial deposition process
Data Source
AI summary
A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.