Transistor Package with Separate Sense Chip for Current Sensing
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Solution Overview
Problem
Conventional current sensing in transistor packages often increases chip cost and has limited versatility, as it either uses a shunt resistor or dedicates transistor cells for sensing, which can restrict application and accuracy.
Innovation Solution
A transistor package design featuring a separate chip for the load transistor and a sense transistor, with various terminal configurations and sense resistance connections, allowing for flexible and cost-effective load current sensing through voltage drop measurement or current mirroring methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a shunt resistor is used for current sensing, then current measurement is achieved, but chip cost increases and application versatility is limited
Solution Approach 1:
The patent separates the load transistor and sense transistor onto different chips. The sense transistor chip is dedicated solely to current sensing functions, while the load transistor chip handles power switching. This segmentation allows each chip to be optimized for its specific function and enables versatile applications by independently selecting appropriate sense transistor configurations.
Solution Approach 2:
The sense transistor chip can be configured for multiple sensing methods including voltage drop measurement and current mirroring. The package supports both first package type (with sense transistor chip) and second package type (without sense transistor chip), allowing the same load transistor chip to be used across different applications with varying sensing requirements.
2Measurement precision
If transistor cells are dedicated for sense transistor, then current sensing is implemented, but chip cost increases and application restrictions are imposed
Solution Approach 1:
The patent separates the load transistor and sense transistor onto different chips. The sense transistor chip is dedicated solely to current sensing functions, while the load transistor chip handles power switching. This segmentation allows each chip to be optimized for its specific function and enables versatile applications by independently selecting appropriate sense transistor configurations.
Solution Approach 2:
The sense transistor creates a mirror current that copies the load current characteristics. This current mirroring technique allows accurate current sensing without requiring the sense transistor to handle the full load current, reducing the size and cost of the sense transistor chip while maintaining measurement accuracy.
3Measurement precision
If sense transistor is integrated on the same chip, then current sensing is achieved, but versatility is limited by consumer application requirements
Solution Approach 1:
The patent separates the load transistor and sense transistor onto different chips. The sense transistor chip is dedicated solely to current sensing functions, while the load transistor chip handles power switching. This segmentation allows each chip to be optimized for its specific function and enables versatile applications by independently selecting appropriate sense transistor configurations.
Solution Approach 2:
The patent provides dynamic configurability through two package types. The first package type includes a sense transistor chip for applications requiring current mirroring, while the second package type omits the sense transistor chip for applications using external sensing. This dynamic package configuration allows the same load transistor chip to adapt to different consumer application requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances flexibility and cost-effectiveness while maintaining high measurement accuracy, suitable for diverse applications including electronic fuses and battery management systems, by using separate chips for load and sense transistors with adaptable sense resistance and current regulation techniques.
Implementation Method 1
A voltage drop across the sense resistance may be measured. The voltage drop is indicative of the level of the load current.
Implementation Method 2
a sense current flowing through the sense transistor is regulated for a voltage condition of zero volt across the sense resistance, the sense current being indicative of the level of the load current.
Data Source
Figure 1A~2
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Figure 5
AI summary
A transistor package comprises a first chip which includes a load transistor for switching a load current. The transistor package further comprises a first load terminal, a second load terminal and a control terminal. The first load terminal, the second load terminal and the control terminal are package terminals. The first load terminal is connected to a first load chip pad of the load transistor. The second load terminal is connected to a second load chip pad of the load transistor. The control terminal is connected to a control chip pad of the load transistor. According to a first package type the package further comprises a second chip, the second chip comprising a sense transistor for sensing the load current, and a first type sense terminal connected to the sense transistor, the first type sense terminal being a package terminal. A control chip pad of the sense transistor is connected to the control terminal.