Transistor-Plane Fluidic Cooling for Self-Heating Reduction

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Solution Overview

Problem

Current cooling solutions for semiconductor devices are inefficient and wasteful due to their distance from nanoscale heat sources, leading to significant thermal waste and performance degradation, especially in densely packed data centers where heat management is critical for sustainability and performance.

Innovation Solution

The implementation of nano-fluidic channels within semiconductor devices to directly immerse dielectric liquids in close proximity to transistors for efficient heat removal, with a closed circuit at the transistor level and secondary cooling at the chip surface, utilizing MEMs micro-pumps for fluid circulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional cooling solutions (heatsinks, fans, air-cooling) are used at package or board level, then cooling coverage is provided, but the distance from heat sources is too large resulting in inefficient heat removal and significant thermal waste

Engineering Contradiction:
Improvethermal wasteVSAvoiddistance from heat sources
Core Design Contradiction:
Loss of energyVSLength of stationary object

Solution Approach 1:

The patent transitions from conventional planar cooling at package/board level to three-dimensional cooling channels formed within the transistor stack itself. By etching vertical and horizontal channels through multiple layers of the semiconductor device, the cooling system achieves proximity to heat sources in the z-dimension (vertical), dramatically reducing thermal resistance and energy loss while maintaining structural integrity through layered channel formation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The cooling channels are nested directly within the transistor stack structure, with channels formed through alternating layers of transistors and dielectric materials. This nested configuration allows coolant to flow through the core of the heat-generating structure, maximizing heat removal efficiency while minimizing the distance between coolant and heat sources, thereby reducing thermal waste

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If transistor density is increased for technological progress, then computing power improves, but self-heating effect becomes a global primary source of performance cost and environmental cost

Engineering Contradiction:
Improvecomputing powerVSAvoidself-heating effect
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The transistor stack is segmented into alternating layers of transistors and dielectric materials, with cooling channels formed through these segmented layers. This segmentation allows coolant to access heat sources at multiple levels within the stack, enabling efficient heat removal from high-density transistor arrangements and mitigating self-heating effects that would otherwise limit computing power

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A dielectric coolant is introduced as an intermediary substance that flows through channels formed within the transistor stack. This dielectric coolant serves as a thermal intermediary, absorbing heat from high-density transistors and transporting it to external heat exchangers, thereby enabling sustained high computing power without excessive self-heating

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If robust cooling solutions are implemented to maintain high performance, then performance degradation is prevented, but energy efficiency decreases due to 40% of data center energy dedicated to cooling

Engineering Contradiction:
Improveperformance stabilityVSAvoidcooling energy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Cooling channels are formed and integrated within the transistor stack during the manufacturing process, before the device is operational. This preliminary integration ensures that cooling pathways are already in place when high power densities are achieved, enabling immediate and efficient heat removal without requiring additional energy-intensive cooling infrastructure to be added later

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The transistor stack structure itself is modified to provide its own cooling channels, making the device self-cooling. By forming channels through the dielectric layers surrounding the transistors, the structure serves dual purposes: maintaining electrical isolation between transistors and providing thermal management pathways, thereby reducing the need for separate, energy-intensive cooling systems

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables quasi-instant heat removal and significantly reduces thermal waste, enhancing performance and energy efficiency, particularly in dense 3D integration scenarios, and can lead to increased power density and reduced environmental impact.

Implementation Method 1

filling the cavities with a dielectric fluid such that the dielectric fluid is in proximate thermal contact with the semiconductor devices

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

forming a circulating mechanism to circulate the dielectric fluid from the cavities to a heat dissipation region and back through the cavities

Methodology Applied
Scientific EffectConvection: Convection

Data Source

PatentUS12051638B2Integrated high efficiency transistor cooling
Publication Date: 2024.07.30 TOKYO ELECTRON LTD
  • US12051638B2 patent drawing
  • US12051638B2 patent drawing
  • US12051638B2 patent drawing

AI summary

A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.