Selective Protection Layers for Transistor Gate Replacement Etching

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Solution Overview

Problem

As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in protecting semiconductor nanostructures during gate replacement processes, leading to over-etching and reduced device reliability.

Innovation Solution

The implementation of protection layers selectively deposited on isolation regions by inhibiting their deposition on semiconductor nanostructures, using dangling amino groups or inhibition layers to enhance deposition selectivity, thereby avoiding over-etching and improving device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protection layers are deposited during gate replacement process, then isolation regions are protected from etching losses, but semiconductor nanostructures may also be covered requiring additional removal steps

Engineering Contradiction:
Improvedevice reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies selective deposition to create protection layers only on isolation regions while leaving semiconductor nanostructures exposed. This local differentiation solves the contradiction by providing protection where needed (isolation regions) without the unwanted side effect of covering the nanostructures, thus avoiding additional removal steps and simplifying the overall process.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces an intermediary mechanism (selective deposition process with amino groups) that enables differential protection. The amino groups act as a mediator that prevents deposition on semiconductor nanostructures while allowing deposition on isolation regions, thus resolving the contradiction between protecting isolation regions and maintaining nanostructure accessibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If minimum feature sizes are reduced for increased integration density, then more components can be integrated into a given area, but additional problems arise in protecting semiconductor structures during processing

Engineering Contradiction:
Improveintegration densityVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The selective deposition process creates locally differentiated protection: isolation regions receive protection layers while semiconductor nanostructures remain exposed. This local quality approach enables high integration density processing while maintaining device reliability by preventing etching losses on isolation regions without compromising the integrity of closely-spaced semiconductor structures.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The protection layers are deposited in advance before etching operations during gate replacement. This preliminary protective action ensures that when subsequent etching steps are performed to remove dummy gates and form actual gates, the isolation regions are already protected, preventing etching losses that would compromise device reliability in high-density integrations.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If deposition selectivity is increased between semiconductor nanostructures and isolation regions, then protection layers can be selectively deposited, but requires special surface treatment processes

Engineering Contradiction:
Improvedeposition selectivityVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary surface treatment by introducing amino groups onto semiconductor nanostructures before the deposition step. This preliminary action creates the chemical basis for selective deposition: the amino groups on semiconductor nanostructures prevent protection layer formation, while isolation regions without amino groups receive the protection layers. This approach achieves high deposition selectivity through a single well-defined surface treatment step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the chemical parameter of the semiconductor nanostructure surface by introducing amino groups. This parameter change (chemical functionalization) creates a fundamental difference in surface properties between semiconductor nanostructures and isolation regions, enabling the deposition process to selectively form protection layers only on isolation regions based on chemical rather than just physical differences.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures precise exposure of semiconductor nanostructures during subsequent processing, reducing over-etching and enhancing the reliability of semiconductor devices by maintaining the integrity of isolation regions.

Implementation Method 1

a silicon-carbon precursor that adsorbs on oxygen atoms of the hydroxyl groups

Methodology Applied
Scientific EffectAdsorption: Adsorption

Data Source

PatentUS20250113566A1Transistor protection layers and methods of forming the same
Publication Date: 2025.04.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250113566A1 patent drawing
  • US20250113566A1 patent drawing
  • US20250113566A1 patent drawing

AI summary

Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.