Transistor Reservoir Device with Parasitic-Capacitance Memory
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Solution Overview
Problem
Current reservoir devices for in-memory computing lack an integrated architecture suitable for memory devices and do not effectively utilize short-term memory characteristics for temporal/sequential information processing.
Innovation Solution
A reservoir device comprising a first and second transistor, with a storage node coupled between their gates and sources, allowing for write, read, and refresh operations based on input voltages, and a reservoir array with multiple rows and columns of such devices for parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a reservoir device architecture is designed for in-memory computing, then computational capability is improved, but device integration complexity increases
Solution Approach 1:
The patent combines the reservoir computing functionality directly into the memory device architecture by utilizing the memory cell's inherent capacitance as the storage node, merging computation and memory functions into a single integrated structure. This eliminates the need for separate computational units and reduces overall system complexity.
Solution Approach 2:
The memory cell is designed to perform multiple functions: it serves as both a storage element and a computational unit for reservoir computing operations. The same hardware structure supports both data storage and temporal/sequential information processing, making the device universally applicable for both memory and computation tasks.
2Adaptability or versatility
If short-term memory characteristic is utilized for temporal processing, then information processing capability is improved, but device structure complexity increases
Solution Approach 1:
The memory cell's inherent capacitance is utilized to provide the short-term memory characteristic needed for temporal processing. The device serves itself by using its own physical property (capacitance) to enable computational functionality, rather than requiring additional dedicated components for temporal processing.
Solution Approach 2:
The patent changes the operational parameters of the existing memory cell by applying specific voltage sequences and timing patterns that exploit the capacitance's charge retention property. This allows the cell to exhibit short-term memory behavior without structural modifications, maintaining simplicity while enabling temporal information processing.
3Measurement precision
If voltage state maintenance through parasitic capacitance is implemented, then computational accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent converts the typically harmful effect of parasitic capacitance (which causes charge leakage and requires refresh operations) into a beneficial feature for computational accuracy. The parasitic capacitance is deliberately utilized to maintain voltage states representing computational data, transforming a source of error into a functional element that enhances measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed architecture enables efficient reservoir computing by maintaining voltage states through parasitic capacitance, facilitating temporal/sequential information processing and integration into memory devices.
Implementation Method 1
The proposed architecture enables efficient reservoir computing by maintaining voltage states through parasitic capacitance
Data Source
AI summary
A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.