Transistor Monocrystalline Seed Layer Reduces Base-Collector Capacitance
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Solution Overview
Problem
Conventional transistors used in RF applications, such as bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs), face challenges in achieving high transit frequency and maximum oscillation frequency due to high base-collector junction capacitance, which limits their performance.
Innovation Solution
A transistor design with a narrow in-substrate collector region is implemented, featuring a trench isolation region and a conformal seed layer with a monocrystalline center section wider than the collector region, along with an intrinsic and extrinsic base layer structure that increases the space between the extrinsic base and collector regions, reducing base-collector junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the collector region is made wider to maintain component size, then the transistor can maintain its physical footprint, but the base-collector junction capacitance increases which reduces maximum oscillation frequency
Solution Approach 1:
The patent applies dimensionality change by forming the monocrystalline seed layer section that extends laterally beyond the collector region boundaries in the horizontal plane. This creates an overlapping region in the lateral dimension that allows the extrinsic base to be offset vertically while maintaining electrical connection, thereby reducing capacitance without reducing collector area.
Solution Approach 2:
The monocrystalline seed layer section acts as an intermediary structure between the collector region and the extrinsic base. It provides a lateral extension that enables the extrinsic base to be positioned offset from the collector vertically, creating a spatial separation that reduces capacitance while maintaining electrical connectivity through the seed layer.
2Reliability
If the collector region is narrowed to reduce base-collector junction capacitance, then the maximum oscillation frequency increases, but the physical footprint and component size decrease
Solution Approach 1:
The solution moves the electrical connection function to another dimension by creating a lateral extension of the monocrystalline seed layer. This allows the extrinsic base to be offset vertically from the collector while maintaining electrical connection through the laterally extended seed layer, effectively decoupling the capacitance-reducing vertical offset from the area-reducing narrow collector design.
Solution Approach 2:
The laterally extended monocrystalline seed layer serves as an intermediary that bridges the gap between the narrowed collector region and the offset extrinsic base. It provides both mechanical support and electrical connectivity, enabling the narrowed collector design to achieve reduced capacitance without compromising the overall component footprint.
3Ease of manufacture
If the extrinsic base is positioned directly above the collector region, then the vertical alignment is simplified, but the base-collector junction capacitance increases
Solution Approach 1:
The laterally extended monocrystalline seed layer acts as an intermediary structure that enables the extrinsic base to be offset vertically from the collector while maintaining electrical connection. This intermediary provides both mechanical support and electrical pathways, allowing the extrinsic base to be positioned away from the collector to reduce capacitance without requiring complex alignment procedures.
Solution Approach 2:
The patent changes the spatial parameters by creating a lateral extension of the seed layer beyond the collector boundaries. This parameter change allows the extrinsic base offset distance to be increased, thereby reducing the base-collector junction capacitance while the seed layer maintains electrical connectivity despite the increased horizontal separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces base-collector junction capacitance, thereby enhancing the maximum oscillation frequency without requiring a decrease in the size of other critical components, thus improving the transistor's performance in RF applications.
Implementation Method 1
The monocrystalline center section can be aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process performed during device fabrication)
Implementation Method 2
An intrinsic base layer can be epitaxially deposited on the seed layer such that the resulting intrinsic base layer similarly has a monocrystalline center section that is aligned above and wider than the collector region
Data Source
AI summary
Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.