Transistor Fabrication Using Segmented Crystal Orientation
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Solution Overview
Problem
Conventional methods for forming transistors result in low saturation current and compromised device performance due to low carrier mobility, particularly as critical dimensions decrease and crystal orientation differences between semiconductor layers and substrates lead to increased current leakage.
Innovation Solution
A method involving the formation of a semiconductor layer on a substrate with different crystal orientations, creating stress in the channel region to enhance carrier mobility, along with the optional use of an epitaxial layer and defect-absorbing ions to reduce leakage current and maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form transistors, then manufacturing process is simple, but saturation current is low and device performance is compromised
Solution Approach 1:
The channel region is segmented into multiple crystal orientation regions (first crystal orientation and second crystal orientation) along the longitudinal direction. This segmentation allows different regions to contribute differently to carrier mobility, thereby increasing saturation current while managing the complexity through a systematic structural division.
Solution Approach 2:
Different crystal orientation regions are introduced to provide locally optimized properties. The first crystal orientation region and second crystal orientation region have different orientations relative to the substrate, creating local variations in stress and carrier mobility that collectively enhance saturation current.
2Productivity
If critical dimensions are decreased to improve transistor scaling, then device density increases, but carrier mobility decreases and saturation current is reduced
Solution Approach 1:
The crystal orientation parameter is changed by introducing regions with different orientations (first and second crystal orientations) relative to the substrate. This parameter change maintains or enhances carrier mobility even when critical dimensions are reduced, thereby preserving saturation current in scaled devices.
3Productivity
If stress is applied to promote carrier mobility, then saturation current increases, but current leakage increases due to crystal orientation differences
Solution Approach 1:
The channel is divided into regions with different crystal orientations, where each region provides local stress to promote carrier mobility. By carefully designing the orientation relationships, the patent achieves beneficial stress effects while minimizing leakage caused by orientation mismatches at interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases saturation current and improves device performance by creating stress in the channel region and reducing leakage current through epitaxial layer formation and defect absorption, effectively addressing the limitations of conventional transistor fabrication techniques.
Implementation Method 1
the semiconductor layer and the semiconductor substrate having different crystal orientations
Implementation Method 2
implanting defect absorbing ions into the epitaxial layer to form defect absorbing ions in the epitaxial layer, the defect absorbing ions being used for absorbing the defects in a channel region
Data Source
AI summary
The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.