Transistor Structure Fabrication With Selective ALD and Vacancy Repair
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the size of transistors and interconnects while maintaining performance, due to limitations in materials and processes used in current semiconductor device fabrication.
Innovation Solution
A method is developed to fabricate a transistor structure by selectively depositing a stack of a ferroelectric layer, a barrier layer, and a channel layer on a gate electrode using atomic layer deposition (ALD), with a monolayer precursor forming a protection layer to prevent deposition on unwanted areas and an O2 and/or O3 plasma treatment to fill oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form transistor layers, then deposition coverage is achieved, but selective deposition on specific regions is poor and oxygen vacancies occur
Solution Approach 1:
A monolayer is formed on the dielectric layer surface before the ALD deposition process. This preliminary action creates a protective barrier that prevents deposition on unwanted areas while allowing selective deposition on the gate electrode, thereby improving manufacturing precision without causing oxygen vacancies
Solution Approach 2:
The monolayer acts as an intermediary between the ALD deposition process and the dielectric layer. It enables selective deposition by being selectively removed or differentially resistant to deposition, solving both the selectivity and oxygen vacancy issues simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the selective deposition of layers and resolves oxygen vacancy issues, leading to enhanced performance of the resulting transistors.
Implementation Method 1
forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode
Implementation Method 2
an O2 and/or O3 plasma treatment is performed to remove the monolayer, and meanwhile fill-up an oxygen vacancy of a revealed surface of the dielectric layer
Data Source
AI summary
A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.