Bottom-Gate Transistor Self-Alignment via Electric Field Deposition
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Solution Overview
Problem
Existing bottom-gate transistors face challenges in self-aligning the active layer and the gate due to the opaque gate insulating layer, which affects the effective self-alignment during the dry etching process.
Innovation Solution
A manufacturing method for transistors that involves dispersing active layer material in a polar or non-polar solvent, forming a charged solution, and using an auxiliary electrode to create a horizontal or vertical electric field between the auxiliary electrode and the bottom gate. This electric field deposits the active layer material onto the gate insulating layer, allowing for self-alignment of the active layer and the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching is used to pattern the active layer, then the active layer can be formed with defined patterns, but the opaque gate insulating layer prevents effective self-alignment between the active layer and the gate
Solution Approach 1:
The patent replaces the mechanical/chemical dry etching process with an electric field-based deposition process. By applying an electric field between the gate and auxiliary electrode, charged active layer materials are directly deposited onto the gate insulating layer in a self-aligned manner, eliminating the need for opaque layer interference during patterning.
Solution Approach 2:
The patent changes the electrical parameters of the system by introducing charged active layer materials and applying controlled electric fields. By varying the voltage between the gate and auxiliary electrode, the deposition process achieves precise self-alignment without relying on optical transparency of the gate insulating layer.
2Reliability
If the gate insulating layer is made opaque to protect the gate, then the gate is protected from damage, but self-alignment of the active layer and gate becomes ineffective
Solution Approach 1:
The patent introduces an auxiliary electrode as an intermediary component that mediates the self-alignment process. The auxiliary electrode, positioned adjacent to the gate, creates an electric field that guides the deposition of active layer materials directly onto the gate insulating layer, enabling self-alignment without requiring optical transparency.
Solution Approach 2:
The patent substitutes the optical alignment mechanism (which requires transparent insulating layers) with an electric field-based alignment mechanism. The electric field generated between the gate and auxiliary electrode directly guides the charged active layer materials to the correct positions, maintaining gate protection while achieving precise self-alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves self-alignment of the active layer and the gate, ensuring that their orthographic projections completely overlap on the base substrate, thereby improving the manufacturing process of bottom-gate transistors.
Implementation Method 1
electrifying the gate and the auxiliary electrode to form an electric field between the auxiliary electrode and the gate; wherein an electrical property of the gate is opposite to an electrical property of the active layer material in the solution, and the active layer material is deposited on the gate insulating layer under an action of the electric field
Data Source
AI summary
The present application provides a manufacturing method of a transistor, including: providing a substrate, a solution, an active layer material and an auxiliary electrode; the active layer material is dispersed in the solution, and the active layer material is charged; positioning the auxiliary electrode on one side of the substrate; positioning the solution between the auxiliary electrode and the gate insulating layer; and electrifying the gate and the auxiliary electrode; an electrical property of the gate is opposite to an electrical property of the active layer material, and the active layer material is deposited on the gate insulating layer under an action of the electric field to form a source layer.