Source Drain Extension Doping for Transistor Series Resistance Reduction
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Solution Overview
Problem
In scaled-down transistors, inaccurate dopant placement and gradual dopant profiles lead to poor transistor gate control and increased series resistance, degrading performance despite geometrical scaling advancements.
Innovation Solution
The introduction of a conductive gate structure with source and/or drain extension regions doped with a first dopant, such as tin, and a second dopant, such as gallium, to modify the lattice structure and reduce series resistance, implemented through hot ion implantation techniques at elevated temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometrical scaling of transistor components is performed, then transistor density is increased, but dopant placement accuracy deteriorates
Solution Approach 1:
The patent uses preliminary action by forming extension regions with high dopant concentration before the main source/drain doping step. This pre-positioning of dopants in extension regions ensures accurate dopant placement even as transistor dimensions are scaled down, maintaining manufacturing precision while enabling higher density.
2Ease of manufacture
If diffused junctions with gradual dopant profiles are used, then manufacturing is simplified, but transistor gate control is degraded
Solution Approach 1:
The patent applies local quality by creating abrupt dopant profiles in extension regions through selective doping, while maintaining simpler processing elsewhere. The abrupt profile in extension regions provides sharp junctions that improve gate control, while the overall process remains manufacturable through localized complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces lateral resistance in transistors while maintaining improved gate control, as evidenced by increased solubility and reduced carrier scattering, enhancing overall transistor performance.
Implementation Method 1
the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions
Implementation Method 2
implemented through hot ion implantation techniques at elevated temperatures
Data Source
AI summary
A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.