Transistor Shield Structure Reduces Feedback Capacitance
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Solution Overview
Problem
High power semiconductor devices with field effect transistors (FETs) face stability and gain reduction due to parasitic feedback capacitance from interdigitated drain and gate runners, which affects amplifier performance.
Innovation Solution
A shield structure is implemented between the gate and drain runners, comprising longitudinally aligned shield traces in the first conductive layer to block electric fields and minimize additional capacitance, thereby reducing feedback capacitance and improving gain and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interdigitated drain and gate runners are used to connect FET terminals, then device connectivity and signal transmission are achieved, but parasitic feedback capacitance is introduced that reduces amplifier stability and gain
Solution Approach 1:
A shield structure is introduced as an intermediary element between the drain and gate runners. This shield comprises conductive traces positioned in an intermediate conductive layer, electrically connected to ground, that act as a mediator to block parasitic capacitive coupling between the drain and gate runners, thereby improving amplifier stability without affecting the functional connectivity of the original runners
Solution Approach 2:
The solution adds a new dimensional layer (intermediate conductive layer) between the existing drain and gate runner layers. By introducing conductive shield traces in this intermediate layer that are grounded, the patent creates a three-dimensional shielding structure that blocks parasitic capacitance paths without altering the planar layout of the original runners
2Reliability
If shield structure is added between gate and drain runners to reduce feedback capacitance, then amplifier gain and stability are improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The intermediate conductive layer is designed to serve multiple functions: it provides the shield structure for parasitic capacitance reduction, maintains grounding references for RF signals, and can be integrated with existing interconnect layers. This multi-functionality reduces the need for additional dedicated shielding structures, thereby limiting the increase in device complexity
3Object-generated harmful factors
If shield traces are positioned between gate fingers and drain, then feedback capacitance is reduced, but additional capacitance contributions from the shield structure itself are introduced
Solution Approach 1:
The shield structure uses local grounding connections at specific positions along the shield traces rather than continuous grounding. This localized approach creates effective parasitic capacitance blocking zones where needed while minimizing the total capacitance of the shield structure itself, thereby reducing energy losses compared to extensive continuous grounding schemes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shield structure effectively reduces feedback capacitance, enhancing the gain and stability of the FETs, while minimizing additional capacitance contributions and enabling die size reduction for module applications.
Implementation Method 1
The shield structure is configured to block electric fields between the input signal tapped from a runner and the output signal carried to another runner of the transistor
Data Source
AI summary
A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.