Power Transistor Short-Circuit Protection via Adaptive Blanking
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Solution Overview
Problem
Existing power management chips face challenges in effectively preventing current accumulation in power transistors during output short-circuits, leading to potential breakdowns, as they often require complex adjustments and are prone to false triggering during startup.
Innovation Solution
An output short-circuit protection method that uses period-wise overcurrent protection with leading-edge blanking time, detects current accumulation, and shortens or cancels leading-edge blanking time during a regulation interval to prevent excessive current flow, thereby reducing the risk of transistor damage without needing system clock adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automatic restart or clock shutdown measures are used for output short-circuit protection, then the power management chip can be protected from breakdown, but the implementation becomes complex and false triggering occurs during chip start-up
Solution Approach 1:
The patent extracts the protection function from complex system-level operations (automatic restart, clock shutdown) and implements it at the circuit level using a dedicated detection module that monitors current accumulation independently. This separates the protection function from the main control logic, avoiding false triggering during startup while maintaining reliability.
Solution Approach 2:
The patent introduces an intermediary detection module that specifically monitors current accumulation in the power transistor. This intermediary component acts as a dedicated sensor between the power transistor and the control logic, providing accurate fault detection without being affected by startup transients that cause false triggering in other protection schemes.
2Reliability
If automatic restart or clock shutdown measures are used for output short-circuit protection, then the power management chip can be protected from breakdown, but false triggering of automatic restart happens during chip start-up
Solution Approach 1:
The detection module autonomously monitors current accumulation and triggers protection without requiring external intervention or complex control logic. The module self-activates when current accumulation is detected and automatically disables the power transistor, providing protection that is both reliable and simple to implement without affecting startup operations.
3Productivity
If no output short-circuit protection measure is taken, then the power supply can operate at maximum switching frequency with full power, but current accumulation in the power transistor exceeds permissible limits causing breakdown
Solution Approach 1:
The patent implements a feedback mechanism where the detection module continuously monitors current accumulation in the power transistor and provides feedback to the control logic. When current accumulation exceeds safe limits, the feedback triggers immediate protection action, allowing the power supply to operate at full capacity during normal conditions while ensuring transistor safety during fault conditions.
Data Source
AI summary
An output short-circuit protection method, a power management chip and a switched-mode power supply are disclosed. When current accumulation has occurred in a power transistor, the number of consecutive current pulses during which the current accumulation occurred is counted. Upon the number of consecutive current pulses reaches a preset value, a regulation interval spanning switching periods is triggered, for at least some of the switching periods, the leading-edge blanking time is shortened or cancelled. In this way, an excessively large current flowing through the power transistor is prevented. Compared with existing fault response measures for power management chips, restart of the power supply and adjustment of the system timing are not needed, allowing easier implementation. Further, the automatic restart during chip start up due to false triggering as found in the existing measures for power management chips is circumvented.