Transistor Source Drain Silicide Interface Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for producing transistors with source and drain areas made of metal-semiconductor compounds face challenges in precise control over silicidation kinetics and prevention of silicidation under the gate electrode, leading to difficulties in achieving close interface proximity with the channel structure.
Innovation Solution
A method involving the formation of lateral protection areas to prevent lateral silicidation, followed by the deposition of a metal layer and thermal annealing to create metal-semiconductor compound regions on either side of the gate, allowing for precise definition of the interface with the channel structure without encroaching on the gate area, and subsequent formation of insulating spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lateral silicidation is implemented to reduce channel access resistance, then the interface between silicided regions and channel structure can be brought closer, but precise control over the stopping of silicidation becomes difficult and silicidation of the channel area may occur
Solution Approach 1:
The patent applies preliminary action by forming protective layers (such as oxide or nitride layers) on the gate electrode and channel structure before performing silicidation. These protective layers are deposited in advance to prevent unwanted silicidation reactions, allowing the silicided regions to be formed close to the channel without encroaching on the gate or channel area. The protective layers are subsequently removed to reveal precisely defined interfaces.
2Productivity
If lateral silicidation kinetics are increased to improve interface proximity, then contact resistance is reduced, but control over the silicidation process becomes more difficult
Solution Approach 1:
The patent applies local quality by creating different surface conditions in different regions of the substrate. Protective layers are selectively formed on the gate and channel areas, while the source and drain regions are left exposed or treated differently. This allows silicidation to proceed rapidly in the source and drain regions where it is desired, while the protected regions remain unaffected, achieving both high productivity and precise boundary definition.
3Reliability
If the interface between silicided regions and channel structure is brought closer to reduce contact resistance, then transistor performance is improved, but the risk of silicidation encroaching on the gate area increases
Solution Approach 1:
The patent uses protective layers as intermediary substances between the silicided regions and the gate/channel structure. These intermediary layers (such as silicon oxide or silicon nitride) physically separate the reactive metal from the regions that should not be silicided, allowing the interface to be positioned very close to the channel while preventing any harmful silicidation of the gate or channel area. The intermediaries are removed after serving their protective function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the interface between silicided regions and the channel, reducing contact resistance and preventing electrostatic coupling, while allowing the formation of superconducting properties in the metal-semiconductor compound regions.
Implementation Method 1
carrying out at least one first thermal annealing so as to form, in the active area, regions based on a metal material-semiconductor material compound
Implementation Method 2
carrying out at least one first thermal annealing so as to form, in the active area, regions based on a metal material-semiconductor material compound
Data Source
AI summary
A method for producing a transistor includes producing on a substrate provided with a semiconductor surface layer in which an active area can be formed, a gate block arranged on the active area. Lateral protection areas are formed against lateral faces of the gate block. Source and drain regions based on a metal material-semiconductor material compound are formed on either side of the gate and in the continuation of a portion located facing the gate block. Insulating spacers are formed on either side of the gate resting on the regions based on a metal material-semiconductor material compound.